Lines Matching full:closed
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
20 * to the supply voltage. In closed-loop mode, when configured with a
65 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */
101 /* DFLL_OUTPUT_CFG: closed loop mode control registers */
121 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */
154 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */
490 * and closed-loop mode, or vice versa.
878 * frequency represented by @req. DFLL must be in closed-loop mode.
906 * settings. In closed-loop mode, update new settings immediately to
908 * until the next switch to closed loop. Returns 0 upon success,
937 * DFLL enable/disable & open-loop <-> closed-loop transitions
1009 * dfll_lock - switch from open-loop to closed-loop mode
1050 * dfll_unlock - switch from closed-loop to open-loop mode
1082 * When the DFLL is being controlled by the CCF, always enter closed loop
1248 * closed-loop mode, and takes the output scaler setting into account.
1393 * program parameters for the closed loop integrator, DVCO tuning,
1548 * DFLL clock is enabled later in closed loop mode by CPUFreq
1642 * In this case closed loop output is controlling duty cycle directly. The s/w