1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
33 	struct device *dev = clk_dev->dev;  in tegra_clock_set_pd_state()
34 	struct dev_pm_opp *opp;  in tegra_clock_set_pd_state()  local
37 	opp = dev_pm_opp_find_freq_ceil(dev, &rate);  in tegra_clock_set_pd_state()
38 	if (opp == ERR_PTR(-ERANGE)) {  in tegra_clock_set_pd_state()
47 		dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate);  in tegra_clock_set_pd_state()
48 		opp = dev_pm_opp_find_freq_floor(dev, &rate);  in tegra_clock_set_pd_state()
51 	if (IS_ERR(opp)) {  in tegra_clock_set_pd_state()
52 		dev_err(dev, "failed to find OPP for %luHz: %pe\n", rate, opp);  in tegra_clock_set_pd_state()
53 		return PTR_ERR(opp);  in tegra_clock_set_pd_state()
56 	pstate = dev_pm_opp_get_required_pstate(opp, 0);  in tegra_clock_set_pd_state()
57 	dev_pm_opp_put(opp);  in tegra_clock_set_pd_state()
71 	mutex_lock(&clk_dev->lock);  in tegra_clock_change_notify()
74 		if (cnd->new_rate > cnd->old_rate)  in tegra_clock_change_notify()
75 			err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);  in tegra_clock_change_notify()
79 		err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate);  in tegra_clock_change_notify()
83 		if (cnd->new_rate < cnd->old_rate)  in tegra_clock_change_notify()
84 			err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate);  in tegra_clock_change_notify()
90 	mutex_unlock(&clk_dev->lock);  in tegra_clock_change_notify()
100 	mutex_lock(&clk_dev->lock);  in tegra_clock_sync_pd_state()
102 	rate = clk_hw_get_rate(clk_dev->hw);  in tegra_clock_sync_pd_state()
105 	mutex_unlock(&clk_dev->lock);  in tegra_clock_sync_pd_state()
114 	struct device *dev = &pdev->dev;  in tegra_clock_probe()
118 	if (!dev->pm_domain)  in tegra_clock_probe()
119 		return -EINVAL;  in tegra_clock_probe()
123 		return -ENOMEM;  in tegra_clock_probe()
129 	clk_dev->dev = dev;  in tegra_clock_probe()
130 	clk_dev->hw = __clk_get_hw(clk);  in tegra_clock_probe()
131 	clk_dev->clk_nb.notifier_call = tegra_clock_change_notify;  in tegra_clock_probe()
132 	mutex_init(&clk_dev->lock);  in tegra_clock_probe()
139 	 * hence we don't use the common OPP helper that initializes OPP  in tegra_clock_probe()
140 	 * state. For some clocks common OPP helper may fail to find ceil  in tegra_clock_probe()
147 	err = clk_notifier_register(clk, &clk_dev->clk_nb);  in tegra_clock_probe()
165 	clk_notifier_unregister(clk, &clk_dev->clk_nb);  in tegra_clock_probe()
173  * NOIRQ phase. We will keep clocks resumed during suspend to mitigate this
175  * perspective since voltage is kept at a nominal level during suspend anyways.
182 	{ .compatible = "nvidia,tegra20-sclk" },
183 	{ .compatible = "nvidia,tegra30-sclk" },
184 	{ .compatible = "nvidia,tegra30-pllc" },
185 	{ .compatible = "nvidia,tegra30-plle" },
186 	{ .compatible = "nvidia,tegra30-pllm" },
192 		.name = "tegra-clock",