1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
29 	void __iomem	*reg;  member
38 	u32 reg;  in tcon_ch1_disable()  local
40 	spin_lock_irqsave(&tclk->lock, flags);  in tcon_ch1_disable()
41 	reg = readl(tclk->reg);  in tcon_ch1_disable()
42 	reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);  in tcon_ch1_disable()
43 	writel(reg, tclk->reg);  in tcon_ch1_disable()
44 	spin_unlock_irqrestore(&tclk->lock, flags);  in tcon_ch1_disable()
51 	u32 reg;  in tcon_ch1_enable()  local
53 	spin_lock_irqsave(&tclk->lock, flags);  in tcon_ch1_enable()
54 	reg = readl(tclk->reg);  in tcon_ch1_enable()
55 	reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;  in tcon_ch1_enable()
56 	writel(reg, tclk->reg);  in tcon_ch1_enable()
57 	spin_unlock_irqrestore(&tclk->lock, flags);  in tcon_ch1_enable()
65 	u32 reg;  in tcon_ch1_is_enabled()  local
67 	reg = readl(tclk->reg);  in tcon_ch1_is_enabled()
68 	return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);  in tcon_ch1_is_enabled()
74 	u32 reg;  in tcon_ch1_get_parent()  local
76 	reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;  in tcon_ch1_get_parent()
77 	reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;  in tcon_ch1_get_parent()
79 	return reg;  in tcon_ch1_get_parent()
86 	u32 reg;  in tcon_ch1_set_parent()  local
88 	spin_lock_irqsave(&tclk->lock, flags);  in tcon_ch1_set_parent()
89 	reg = readl(tclk->reg);  in tcon_ch1_set_parent()
90 	reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);  in tcon_ch1_set_parent()
91 	reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;  in tcon_ch1_set_parent()
92 	writel(reg, tclk->reg);  in tcon_ch1_set_parent()
93 	spin_unlock_irqrestore(&tclk->lock, flags);  in tcon_ch1_set_parent()
119 			    (rate - tmp_rate) < (rate - best_rate)) {  in tcon_ch1_calc_divider()
138 	long best_rate = -EINVAL;  in tcon_ch1_determine_rate()
152 		tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,  in tcon_ch1_determine_rate()
156 		    (req->rate - tmp_rate) < (req->rate - best_rate)) {  in tcon_ch1_determine_rate()
158 			req->best_parent_rate = parent_rate;  in tcon_ch1_determine_rate()
159 			req->best_parent_hw = parent;  in tcon_ch1_determine_rate()
166 	req->rate = best_rate;  in tcon_ch1_determine_rate()
174 	u32 reg;  in tcon_ch1_recalc_rate()  local
176 	reg = readl(tclk->reg);  in tcon_ch1_recalc_rate()
178 	parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;  in tcon_ch1_recalc_rate()
180 	if (reg & TCON_CH1_SCLK1_HALF_BIT)  in tcon_ch1_recalc_rate()
193 	u32 reg;  in tcon_ch1_set_rate()  local
197 	spin_lock_irqsave(&tclk->lock, flags);  in tcon_ch1_set_rate()
198 	reg = readl(tclk->reg);  in tcon_ch1_set_rate()
199 	reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);  in tcon_ch1_set_rate()
200 	reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;  in tcon_ch1_set_rate()
203 		reg |= TCON_CH1_SCLK1_HALF_BIT;  in tcon_ch1_set_rate()
205 	writel(reg, tclk->reg);  in tcon_ch1_set_rate()
206 	spin_unlock_irqrestore(&tclk->lock, flags);  in tcon_ch1_set_rate()
227 	const char *clk_name = node->name;  in tcon_ch1_setup()
228 	struct clk_init_data init;  in tcon_ch1_setup()  local
232 	void __iomem *reg;  in tcon_ch1_setup()  local
235 	of_property_read_string(node, "clock-output-names", &clk_name);  in tcon_ch1_setup()
237 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));  in tcon_ch1_setup()
238 	if (IS_ERR(reg)) {  in tcon_ch1_setup()
253 	init.name = clk_name;  in tcon_ch1_setup()
254 	init.ops = &tcon_ch1_ops;  in tcon_ch1_setup()
255 	init.parent_names = parents;  in tcon_ch1_setup()
256 	init.num_parents = TCON_CH1_SCLK2_PARENTS;  in tcon_ch1_setup()
257 	init.flags = CLK_SET_RATE_PARENT;  in tcon_ch1_setup()
259 	tclk->reg = reg;  in tcon_ch1_setup()
260 	tclk->hw.init = &init;  in tcon_ch1_setup()
261 	spin_lock_init(&tclk->lock);  in tcon_ch1_setup()
263 	clk = clk_register(NULL, &tclk->hw);  in tcon_ch1_setup()
282 	iounmap(reg);  in tcon_ch1_setup()
287 CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",