clk/sunxi/clk-a20-gmac.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
6  * Copyright 2013 Chen-Yu Tsai
7  * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29  * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34  *  MII TX clock from PHY >-----|___________    _________|----> to GMAC core
35  *  GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36  *  Ext. 125MHz RGMII TX clk >--|__divider__/            |
43  * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
44  * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
45  * select the appropriate source and gate/ungate the output to the PHY.
49  * able to send traffic out. The GMAC driver should set the clock rate and
50  * enable/disable this clock to configure the required state. The clock
51  * driver then responds by auto-reparenting the clock.
58 	const char *clk_name = node->name;  in sun7i_a20_gmac_clk_setup()
62 	if (of_property_read_string(node, "clock-output-names", &clk_name))  in sun7i_a20_gmac_clk_setup()
83 	gate->reg = reg;  in sun7i_a20_gmac_clk_setup()
84 	gate->bit_idx = SUN7I_A20_GMAC_GPIT;  in sun7i_a20_gmac_clk_setup()
85 	gate->lock = &gmac_lock;  in sun7i_a20_gmac_clk_setup()
86 	mux->reg = reg;  in sun7i_a20_gmac_clk_setup()
87 	mux->mask = SUN7I_A20_GMAC_MASK;  in sun7i_a20_gmac_clk_setup()
88 	mux->table = sun7i_a20_gmac_mux_table;  in sun7i_a20_gmac_clk_setup()
89 	mux->lock = &gmac_lock;  in sun7i_a20_gmac_clk_setup()
93 			&mux->hw, &clk_mux_ops,  in sun7i_a20_gmac_clk_setup()
95 			&gate->hw, &clk_gate_ops,  in sun7i_a20_gmac_clk_setup()
112 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",