clk/sunxi/clk-a20-gmac.c

29  * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34  *  MII TX clock from PHY >-----|___________    _________|----> to GMAC core
35  *  GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
39  * The external 125 MHz reference is optional, i.e. GMAC can use its
40  * internal TX clock just fine. The A31 GMAC clock module does not have
43  * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
44  * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
47  * Only the GMAC should use this clock. Altering the clock so that it doesn't
48  * match the GMAC's operation parameters will result in the GMAC not being
49  * able to send traffic out. The GMAC driver should set the clock rate and
74 	/* gmac clock requires exactly 2 parents */  in sun7i_a20_gmac_clk_setup()
112 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",