clk/sunxi/clk-a10-pll2.c

16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 	prediv_clk = clk_register_divider(NULL, "pll2-prediv",  in sun4i_pll2_setup()
73 	/* Setup the gate part of the PLL2 */  in sun4i_pll2_setup()
82 	/* Setup the multiplier part of the PLL2 */  in sun4i_pll2_setup()
95 	base_clk = clk_register_composite(NULL, "pll2-base",  in sun4i_pll2_setup()
109 	 * PLL2-1x  in sun4i_pll2_setup()
130 	 * PLL2-2x  in sun4i_pll2_setup()
133 	 * a fixed divider from the PLL2 base clock.  in sun4i_pll2_setup()
143 	/* PLL2-4x */  in sun4i_pll2_setup()
152 	/* PLL2-8x */  in sun4i_pll2_setup()
186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",