1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
20 	u8 delay;  in ccu_phase_get_phase()  local
22 	reg = readl(phase->common.base + phase->common.reg);  in ccu_phase_get_phase()
23 	delay = (reg >> phase->shift);  in ccu_phase_get_phase()
24 	delay &= (1 << phase->width) - 1;  in ccu_phase_get_phase()
26 	if (!delay)  in ccu_phase_get_phase()
29 	/* Get our parent clock, it's the one that can adjust its rate */  in ccu_phase_get_phase()
32 		return -EINVAL;  in ccu_phase_get_phase()
37 		return -EINVAL;  in ccu_phase_get_phase()
42 		return -EINVAL;  in ccu_phase_get_phase()
47 		return -EINVAL;  in ccu_phase_get_phase()
49 	/* Get our parent clock divider */  in ccu_phase_get_phase()
53 	return delay * step;  in ccu_phase_get_phase()
63 	u8 delay;  in ccu_phase_set_phase()  local
65 	/* Get our parent clock, it's the one that can adjust its rate */  in ccu_phase_set_phase()
68 		return -EINVAL;  in ccu_phase_set_phase()
73 		return -EINVAL;  in ccu_phase_set_phase()
78 		return -EINVAL;  in ccu_phase_set_phase()
83 		return -EINVAL;  in ccu_phase_set_phase()
95 		 * Since our parent clock is only a divider, and the  in ccu_phase_set_phase()
101 		 * of period we want to outphase our clock from, and  in ccu_phase_set_phase()
102 		 * the divider set by our parent clock.  in ccu_phase_set_phase()
105 		delay = DIV_ROUND_CLOSEST(degrees, step);  in ccu_phase_set_phase()
107 		delay = 0;  in ccu_phase_set_phase()
110 	spin_lock_irqsave(phase->common.lock, flags);  in ccu_phase_set_phase()
111 	reg = readl(phase->common.base + phase->common.reg);  in ccu_phase_set_phase()
112 	reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);  in ccu_phase_set_phase()
113 	writel(reg | (delay << phase->shift),  in ccu_phase_set_phase()
114 	       phase->common.base + phase->common.reg);  in ccu_phase_set_phase()
115 	spin_unlock_irqrestore(phase->common.lock, flags);  in ccu_phase_set_phase()