clk/sunxi-ng/ccu-sun8i-h3.c

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
26 #include "ccu-sun8i-h3.h"
28 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
43  * With sigma-delta modulation for fractional-N on the audio PLL,
57 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
81 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
93 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
102 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
108 					   2,		/* post-div */
111 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
123 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
129 					   2,		/* post-div */
132 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
145 					     "pll-cpux" , "pll-cpux" };
152 					     "axi" , "pll-periph0" };
188 					     "pll-periph0" , "pll-periph0" };
195 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
210 		.hw.init	= CLK_HW_INIT_PARENTS("ahb2",
217 static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
219 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
221 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
223 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
225 static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
227 static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
229 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
231 static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb2",
233 static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
235 static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
237 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
239 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
241 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
243 static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
245 static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb2",
247 static SUNXI_CCU_GATE(bus_ehci2_clk,	"bus-ehci2",	"ahb2",
249 static SUNXI_CCU_GATE(bus_ehci3_clk,	"bus-ehci3",	"ahb2",
251 static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
253 static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb2",
255 static SUNXI_CCU_GATE(bus_ohci2_clk,	"bus-ohci2",	"ahb2",
257 static SUNXI_CCU_GATE(bus_ohci3_clk,	"bus-ohci3",	"ahb2",
260 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
262 static SUNXI_CCU_GATE(bus_tcon0_clk,	"bus-tcon0",	"ahb1",
264 static SUNXI_CCU_GATE(bus_tcon1_clk,	"bus-tcon1",	"ahb1",
266 static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
268 static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
270 static SUNXI_CCU_GATE(bus_tve_clk,	"bus-tve",	"ahb1",
272 static SUNXI_CCU_GATE(bus_hdmi_clk,	"bus-hdmi",	"ahb1",
274 static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
276 static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
278 static SUNXI_CCU_GATE(bus_msgbox_clk,	"bus-msgbox",	"ahb1",
280 static SUNXI_CCU_GATE(bus_spinlock_clk,	"bus-spinlock",	"ahb1",
283 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
285 static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
287 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
289 static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
291 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
293 static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
295 static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
298 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
300 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
302 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
304 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
306 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
308 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
310 static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
312 static SUNXI_CCU_GATE(bus_scr0_clk,	"bus-scr0",	"apb2",
314 static SUNXI_CCU_GATE(bus_scr1_clk,	"bus-scr1",	"apb2",
317 static SUNXI_CCU_GATE(bus_ephy_clk,	"bus-ephy",	"ahb1",
319 static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
332 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
333 						     "pll-periph1" };
377 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
406 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
407 					    "pll-audio-2x", "pll-audio" };
417 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
420 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
422 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
424 static SUNXI_CCU_GATE(usb_phy2_clk,	"usb-phy2",	"osc24M",
426 static SUNXI_CCU_GATE(usb_phy3_clk,	"usb-phy3",	"osc24M",
428 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc24M",
430 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"osc24M",
432 static SUNXI_CCU_GATE(usb_ohci2_clk,	"usb-ohci2",	"osc24M",
434 static SUNXI_CCU_GATE(usb_ohci3_clk,	"usb-ohci3",	"osc24M",
437 /* H3 has broken MDFS hardware, so the mux/divider cannot be changed. */
442 static const char * const h5_dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
446 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
448 static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
450 static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
452 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
455 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
460 static const char * const tcon_parents[] = { "pll-video" };
465 static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
469 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
473 static SUNXI_CCU_GATE(csi_misc_clk,	"csi-misc",	"osc24M",
476 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
477 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
480 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
481 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
484 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
487 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
492 static const char * const hdmi_parents[] = { "pll-video" };
497 static SUNXI_CCU_GATE(hdmi_ddc_clk,	"hdmi-ddc",	"osc24M",
500 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
504 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
626 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
629 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
632 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
635 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
638 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
1047 	desc = of_device_get_match_data(&pdev->dev);  in sun8i_h3_ccu_probe()
1049 		return -EINVAL;  in sun8i_h3_ccu_probe()
1055 	/* Force the PLL-Audio-1x divider to 1 */  in sun8i_h3_ccu_probe()
1060 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, desc);  in sun8i_h3_ccu_probe()
1068 	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,  in sun8i_h3_ccu_probe()
1076 		.compatible = "allwinner,sun8i-h3-ccu",
1080 		.compatible = "allwinner,sun50i-h5-ccu",
1090 		.name			= "sun8i-h3-ccu",
1098 MODULE_DESCRIPTION("Support for the Allwinner H3 CCU");