Lines Matching +full:0 +full:x2c0
29 "osc24M", 0x000,
32 0, 2, /* M */
50 #define SUN8I_H3_PLL_AUDIO_REG 0x008
53 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
54 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
58 "osc24M", 0x008,
60 0, 5, /* M */
62 0x284, BIT(31),
68 "osc24M", 0x0010,
72 0, 4, /* M */
75 270000000, /* frac rate 0 */
82 "osc24M", 0x0018,
84 0, 4, /* M */
87 270000000, /* frac rate 0 */
94 "osc24M", 0x020,
97 0, 2, /* M */
103 "osc24M", 0x028,
112 "osc24M", 0x0038,
114 0, 4, /* M */
117 270000000, /* frac rate 0 */
124 "osc24M", 0x044,
133 "osc24M", 0x0048,
135 0, 4, /* M */
138 270000000, /* frac rate 0 */
147 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
149 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
168 .reg = 0x054,
173 0),
178 { .val = 0, .div = 2 },
185 0x054, 8, 2, apb1_div_table, 0);
189 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
190 0, 5, /* M */
193 0);
201 .shift = 0,
208 .reg = 0x05c,
213 0),
218 0x060, BIT(5), 0);
220 0x060, BIT(6), 0);
222 0x060, BIT(8), 0);
224 0x060, BIT(9), 0);
226 0x060, BIT(10), 0);
228 0x060, BIT(13), 0);
230 0x060, BIT(14), 0);
232 0x060, BIT(17), 0);
234 0x060, BIT(18), 0);
236 0x060, BIT(19), 0);
238 0x060, BIT(20), 0);
240 0x060, BIT(21), 0);
242 0x060, BIT(23), 0);
244 0x060, BIT(24), 0);
246 0x060, BIT(25), 0);
248 0x060, BIT(26), 0);
250 0x060, BIT(27), 0);
252 0x060, BIT(28), 0);
254 0x060, BIT(29), 0);
256 0x060, BIT(30), 0);
258 0x060, BIT(31), 0);
261 0x064, BIT(0), 0);
263 0x064, BIT(3), 0);
265 0x064, BIT(4), 0);
267 0x064, BIT(5), 0);
269 0x064, BIT(8), 0);
271 0x064, BIT(9), 0);
273 0x064, BIT(11), 0);
275 0x064, BIT(12), 0);
277 0x064, BIT(20), 0);
279 0x064, BIT(21), 0);
281 0x064, BIT(22), 0);
284 0x068, BIT(0), 0);
286 0x068, BIT(1), 0);
288 0x068, BIT(5), 0);
290 0x068, BIT(8), 0);
292 0x068, BIT(12), 0);
294 0x068, BIT(13), 0);
296 0x068, BIT(14), 0);
299 0x06c, BIT(0), 0);
301 0x06c, BIT(1), 0);
303 0x06c, BIT(2), 0);
305 0x06c, BIT(16), 0);
307 0x06c, BIT(17), 0);
309 0x06c, BIT(18), 0);
311 0x06c, BIT(19), 0);
313 0x06c, BIT(20), 0);
315 0x06c, BIT(21), 0);
318 0x070, BIT(0), 0);
320 0x070, BIT(7), 0);
323 { .val = 0, .div = 1 },
330 0x074, 0, 2, ths_div_table, BIT(31), 0);
334 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
335 0, 4, /* M */
339 0);
341 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
342 0, 4, /* M */
346 0);
349 0x088, 20, 3, 0);
351 0x088, 8, 3, 0);
353 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
354 0, 4, /* M */
358 0);
361 0x08c, 20, 3, 0);
363 0x08c, 8, 3, 0);
365 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
366 0, 4, /* M */
370 0);
373 0x090, 20, 3, 0);
375 0x090, 8, 3, 0);
378 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
379 0, 4, /* M */
383 0);
385 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
386 0, 4, /* M */
390 0);
392 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
393 0, 4, /* M */
397 0);
399 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
400 0, 4, /* M */
404 0);
409 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
412 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
415 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
418 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
421 0x0cc, BIT(8), 0);
423 0x0cc, BIT(9), 0);
425 0x0cc, BIT(10), 0);
427 0x0cc, BIT(11), 0);
429 0x0cc, BIT(16), 0);
431 0x0cc, BIT(17), 0);
433 0x0cc, BIT(18), 0);
435 0x0cc, BIT(19), 0);
444 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
447 0x100, BIT(0), 0);
449 0x100, BIT(1), 0);
451 0x100, BIT(2), 0);
453 0x100, BIT(3), 0);
457 0x104, 0, 4, 24, 3, BIT(31),
462 0x118, 0, 4, 24, 3, BIT(31),
467 0x120, 0, 4, 24, 3, BIT(31), 0);
471 0x124, 0, 4, 24, 3, BIT(31), 0);
474 0x130, BIT(31), 0);
478 0x134, 16, 4, 24, 3, BIT(31), 0);
482 0x134, 0, 5, 8, 3, BIT(15), 0);
485 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
488 0x140, BIT(31), CLK_SET_RATE_PARENT);
490 0x144, BIT(31), 0);
494 0x150, 0, 4, 24, 2, BIT(31),
498 0x154, BIT(31), 0);
502 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
505 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
640 1, 2, 0);
880 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
881 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
882 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
883 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
885 [RST_MBUS] = { 0x0fc, BIT(31) },
887 [RST_BUS_CE] = { 0x2c0, BIT(5) },
888 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
889 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
890 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
891 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
892 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
893 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
894 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
895 [RST_BUS_TS] = { 0x2c0, BIT(18) },
896 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
897 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
898 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
899 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
900 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
901 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
902 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
903 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
904 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
905 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
906 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
907 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
909 [RST_BUS_VE] = { 0x2c4, BIT(0) },
910 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
911 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
912 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
913 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
914 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
915 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
916 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
917 [RST_BUS_DE] = { 0x2c4, BIT(12) },
918 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
919 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
920 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
921 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
923 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
925 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
926 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
927 [RST_BUS_THS] = { 0x2d0, BIT(8) },
928 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
929 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
930 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
932 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
933 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
934 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
935 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
936 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
937 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
938 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
939 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
943 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
944 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
945 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
946 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
948 [RST_MBUS] = { 0x0fc, BIT(31) },
950 [RST_BUS_CE] = { 0x2c0, BIT(5) },
951 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
952 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
953 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
954 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
955 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
956 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
957 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
958 [RST_BUS_TS] = { 0x2c0, BIT(18) },
959 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
960 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
961 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
962 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
963 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
964 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
965 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
966 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
967 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
968 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
969 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
970 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
972 [RST_BUS_VE] = { 0x2c4, BIT(0) },
973 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
974 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
975 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
976 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
977 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
978 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
979 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
980 [RST_BUS_DE] = { 0x2c4, BIT(12) },
981 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
982 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
983 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
984 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
986 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
988 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
989 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
990 [RST_BUS_THS] = { 0x2d0, BIT(8) },
991 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
992 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
993 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
995 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
996 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
997 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
998 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
999 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1000 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1001 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1002 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
1003 [RST_BUS_SCR1] = { 0x2d8, BIT(20) },
1051 reg = devm_platform_ioremap_resource(pdev, 0); in sun8i_h3_ccu_probe()
1058 writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG); in sun8i_h3_ccu_probe()
1071 return 0; in sun8i_h3_ccu_probe()