Lines Matching +full:0 +full:x060
34 .m = _SUNXI_CCU_DIV(0, 2),
38 .reg = 0x000,
41 0),
57 #define SUN8I_A23_PLL_AUDIO_REG 0x008
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65 "osc24M", 0x008,
67 0, 5, /* M */
69 0x284, BIT(31),
75 "osc24M", 0x010,
77 0, 4, /* M */
80 270000000, /* frac rate 0 */
87 "osc24M", 0x018,
89 0, 4, /* M */
92 270000000, /* frac rate 0 */
99 "osc24M", 0x020,
102 0, 2, /* M */
105 0);
108 "osc24M", 0x028,
117 "osc24M", 0x038,
119 0, 4, /* M */
122 270000000, /* frac rate 0 */
135 #define SUN8I_A23_PLL_MIPI_REG 0x040
137 "pll-video", 0x040,
140 0, 4, /* M */
146 "osc24M", 0x044,
148 0, 4, /* M */
151 270000000, /* frac rate 0 */
158 "osc24M", 0x048,
160 0, 4, /* M */
163 270000000, /* frac rate 0 */
172 0x050, 16, 2, CLK_IS_CRITICAL);
174 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
193 .reg = 0x054,
198 0),
203 { .val = 0, .div = 2 },
210 0x054, 8, 2, apb1_div_table, 0);
214 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
215 0, 5, /* M */
218 0);
221 0x060, BIT(1), 0);
223 0x060, BIT(6), 0);
225 0x060, BIT(8), 0);
227 0x060, BIT(9), 0);
229 0x060, BIT(10), 0);
231 0x060, BIT(13), 0);
233 0x060, BIT(14), 0);
235 0x060, BIT(19), 0);
237 0x060, BIT(20), 0);
239 0x060, BIT(21), 0);
241 0x060, BIT(24), 0);
243 0x060, BIT(26), 0);
245 0x060, BIT(29), 0);
248 0x064, BIT(0), 0);
250 0x064, BIT(4), 0);
252 0x064, BIT(8), 0);
254 0x064, BIT(12), 0);
256 0x064, BIT(14), 0);
258 0x064, BIT(20), 0);
260 0x064, BIT(21), 0);
262 0x064, BIT(22), 0);
264 0x064, BIT(25), 0);
267 0x068, BIT(0), 0);
269 0x068, BIT(5), 0);
271 0x068, BIT(12), 0);
273 0x068, BIT(13), 0);
276 0x06c, BIT(0), 0);
278 0x06c, BIT(1), 0);
280 0x06c, BIT(2), 0);
282 0x06c, BIT(16), 0);
284 0x06c, BIT(17), 0);
286 0x06c, BIT(18), 0);
288 0x06c, BIT(19), 0);
290 0x06c, BIT(20), 0);
293 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
294 0, 4, /* M */
298 0);
300 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
301 0, 4, /* M */
305 0);
308 0x088, 20, 3, 0);
310 0x088, 8, 3, 0);
312 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
313 0, 4, /* M */
317 0);
320 0x08c, 20, 3, 0);
322 0x08c, 8, 3, 0);
324 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
325 0, 4, /* M */
329 0);
332 0x090, 20, 3, 0);
334 0x090, 8, 3, 0);
336 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
337 0, 4, /* M */
341 0);
343 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
344 0, 4, /* M */
348 0);
353 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
356 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
360 0x0cc, BIT(8), 0);
362 0x0cc, BIT(9), 0);
364 0x0cc, BIT(10), 0);
366 0x0cc, BIT(11), 0);
368 0x0cc, BIT(16), 0);
371 0x100, BIT(0), 0);
373 0x100, BIT(1), 0);
375 0x100, BIT(16), 0);
377 0x100, BIT(24), 0);
379 0x100, BIT(26), 0);
383 static const u8 de_table[] = { 0, 2, 3, 5 };
386 0x104, 0, 4, 24, 3, BIT(31), 0);
390 0x10c, 0, 4, 24, 3, BIT(31), 0);
394 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
397 0x118, 24, 3, BIT(31),
401 static const u8 lcd_ch1_table[] = { 0, 2 };
404 0x12c, 0, 4, 24, 2, BIT(31), 0);
408 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
411 0x134, 16, 4, 24, 3, BIT(31), 0);
415 static const u8 csi_mclk_table[] = { 0, 3, 5 };
418 0x134, 0, 5, 8, 3, BIT(15), 0);
421 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
424 0x140, BIT(31), CLK_SET_RATE_PARENT);
426 0x144, BIT(31), 0);
431 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
434 static const u8 dsi_sclk_table[] = { 0, 2 };
437 0x168, 16, 4, 24, 2, BIT(31), 0);
440 static const u8 dsi_dphy_table[] = { 0, 2 };
443 0x168, 0, 4, 8, 2, BIT(15), 0);
447 0x180, 0, 4, 24, 3, BIT(31), 0);
450 0x1a0, 0, 3, BIT(31), 0);
454 0x1b0, 0, 3, 24, 2, BIT(31), 0);
566 1, 2, 0);
569 1, 2, 0);
672 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
673 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
674 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
676 [RST_MBUS] = { 0x0fc, BIT(31) },
678 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
679 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
680 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
681 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
682 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
683 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
684 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
685 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
686 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
687 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
688 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
689 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
690 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
692 [RST_BUS_VE] = { 0x2c4, BIT(0) },
693 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
694 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
695 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
696 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
697 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
698 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
699 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
700 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
702 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
704 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
705 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
706 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
708 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
709 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
710 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
711 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
712 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
713 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
714 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
715 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
733 reg = devm_platform_ioremap_resource(pdev, 0); in sun8i_a23_ccu_probe()
740 writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG); in sun8i_a23_ccu_probe()