Lines Matching full:ahb1
222 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
237 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
248 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
250 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
252 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
254 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
256 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
258 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
260 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
262 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
264 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
266 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
268 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
270 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
272 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
274 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
276 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
278 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
280 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
282 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
284 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
286 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
288 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
290 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
292 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
295 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
297 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
299 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
301 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
303 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
305 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
307 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
309 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
311 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
313 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
315 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
317 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
319 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
321 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
323 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
734 "axi", "ahb1" };
1250 /* Force AHB1 to PLL6 / 3 */ in sun6i_a31_ccu_probe()