clk/sunxi-ng/ccu-sun5i.c

214 		.hw.init	= CLK_HW_INIT_PARENTS("ahb",
228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
241 static SUNXI_CCU_GATE(ahb_otg_clk,	"ahb-otg",	"ahb",
243 static SUNXI_CCU_GATE(ahb_ehci_clk,	"ahb-ehci",	"ahb",
245 static SUNXI_CCU_GATE(ahb_ohci_clk,	"ahb-ohci",	"ahb",
247 static SUNXI_CCU_GATE(ahb_ss_clk,	"ahb-ss",	"ahb",
249 static SUNXI_CCU_GATE(ahb_dma_clk,	"ahb-dma",	"ahb",
251 static SUNXI_CCU_GATE(ahb_bist_clk,	"ahb-bist",	"ahb",
253 static SUNXI_CCU_GATE(ahb_mmc0_clk,	"ahb-mmc0",	"ahb",
255 static SUNXI_CCU_GATE(ahb_mmc1_clk,	"ahb-mmc1",	"ahb",
257 static SUNXI_CCU_GATE(ahb_mmc2_clk,	"ahb-mmc2",	"ahb",
259 static SUNXI_CCU_GATE(ahb_nand_clk,	"ahb-nand",	"ahb",
261 static SUNXI_CCU_GATE(ahb_sdram_clk,	"ahb-sdram",	"ahb",
263 static SUNXI_CCU_GATE(ahb_emac_clk,	"ahb-emac",	"ahb",
265 static SUNXI_CCU_GATE(ahb_ts_clk,	"ahb-ts",	"ahb",
267 static SUNXI_CCU_GATE(ahb_spi0_clk,	"ahb-spi0",	"ahb",
269 static SUNXI_CCU_GATE(ahb_spi1_clk,	"ahb-spi1",	"ahb",
271 static SUNXI_CCU_GATE(ahb_spi2_clk,	"ahb-spi2",	"ahb",
273 static SUNXI_CCU_GATE(ahb_gps_clk,	"ahb-gps",	"ahb",
275 static SUNXI_CCU_GATE(ahb_hstimer_clk,	"ahb-hstimer",	"ahb",
278 static SUNXI_CCU_GATE(ahb_ve_clk,	"ahb-ve",	"ahb",
280 static SUNXI_CCU_GATE(ahb_tve_clk,	"ahb-tve",	"ahb",
282 static SUNXI_CCU_GATE(ahb_lcd_clk,	"ahb-lcd",	"ahb",
284 static SUNXI_CCU_GATE(ahb_csi_clk,	"ahb-csi",	"ahb",
286 static SUNXI_CCU_GATE(ahb_hdmi_clk,	"ahb-hdmi",	"ahb",
288 static SUNXI_CCU_GATE(ahb_de_be_clk,	"ahb-de-be",	"ahb",
290 static SUNXI_CCU_GATE(ahb_de_fe_clk,	"ahb-de-fe",	"ahb",
292 static SUNXI_CCU_GATE(ahb_iep_clk,	"ahb-iep",	"ahb",
294 static SUNXI_CCU_GATE(ahb_gpu_clk,	"ahb-gpu",	"ahb",
1005 	 * Use the peripheral PLL as the AHB parent, instead of CPU /  in sun5i_ccu_init()
1009 	 * clock is AHB.  in sun5i_ccu_init()