clk/sunxi-ng/ccu-sun5i.c

28 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
30 	.m		= _SUNXI_CCU_DIV(0, 2),
33 		.reg		= 0x000,
37 					      0),
53 #define SUN5I_PLL_AUDIO_REG	0x008
56 	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
62 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
68 	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
69 	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
70 					 0x00c, BIT(31)),
72 		.reg		= 0x008,
77 					      0),
83 	.mult		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
87 		.reg		= 0x010,
94 					      0),
100 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
102 	.m		= _SUNXI_CCU_DIV(0, 2),
105 		.reg		= 0x018,
109 					      0),
115 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
118 		.reg		= 0x020,
122 					      0),
126 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
133 		.reg		= 0x020,
136 					      0),
142 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
146 		.reg		= 0x028,
151 					      0),
157 	.mult		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
161 		.reg		= 0x030,
168 					      0),
172 static SUNXI_CCU_GATE(hosc_clk,	"hosc",	"osc24M", 0x050, BIT(0), 0);
174 #define SUN5I_AHB_REG	0x054
188 		.reg		= 0x054,
197 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
213 		.reg		= 0x054,
217 						      0),
222 	{ .val = 0, .div = 2 },
229 			   0x054, 8, 2, apb0_div_table, 0);
232 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
233 			     0, 5,	/* M */
236 			     0);
239 		      0x05c, BIT(0), 0);
242 		      0x060, BIT(0), 0);
244 		      0x060, BIT(1), 0);
246 		      0x060, BIT(2), 0);
248 		      0x060, BIT(5), 0);
250 		      0x060, BIT(6), 0);
252 		      0x060, BIT(7), 0);
254 		      0x060, BIT(8), 0);
256 		      0x060, BIT(9), 0);
258 		      0x060, BIT(10), 0);
260 		      0x060, BIT(13), 0);
262 		      0x060, BIT(14), CLK_IS_CRITICAL);
264 		      0x060, BIT(17), 0);
266 		      0x060, BIT(18), 0);
268 		      0x060, BIT(20), 0);
270 		      0x060, BIT(21), 0);
272 		      0x060, BIT(22), 0);
274 		      0x060, BIT(26), 0);
276 		      0x060, BIT(28), 0);
279 		      0x064, BIT(0), 0);
281 		      0x064, BIT(2), 0);
283 		      0x064, BIT(4), 0);
285 		      0x064, BIT(8), 0);
287 		      0x064, BIT(11), 0);
289 		      0x064, BIT(12), 0);
291 		      0x064, BIT(14), 0);
293 		      0x064, BIT(19), 0);
295 		      0x064, BIT(20), 0);
298 		      0x068, BIT(0), 0);
300 		      0x068, BIT(1), 0);
302 		      0x068, BIT(3), 0);
304 		      0x068, BIT(5), 0);
306 		      0x068, BIT(6), 0);
308 		      0x068, BIT(10), 0);
311 		      0x06c, BIT(0), 0);
313 		      0x06c, BIT(1), 0);
315 		      0x06c, BIT(2), 0);
317 		      0x06c, BIT(16), 0);
319 		      0x06c, BIT(17), 0);
321 		      0x06c, BIT(18), 0);
323 		      0x06c, BIT(19), 0);
327 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
328 				  0, 4,		/* M */
332 				  0);
334 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
335 				  0, 4,		/* M */
339 				  0);
341 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
342 				  0, 4,		/* M */
346 				  0);
348 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
349 				  0, 4,		/* M */
353 				  0);
355 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
356 				  0, 4,		/* M */
360 				  0);
362 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
363 				  0, 4,		/* M */
367 				  0);
369 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
370 				  0, 4,		/* M */
374 				  0);
376 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
377 				  0, 4,		/* M */
381 				  0);
383 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
384 				  0, 4,		/* M */
388 				  0);
390 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
391 				  0, 4,		/* M */
395 				  0);
400 			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
405 			       0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
408 static const u8 keypad_table[] = { 0, 2 };
416 		.reg		= 0x0c4,
420 						      0),
425 		      0x0cc, BIT(6), 0);
427 		      0x0cc, BIT(8), 0);
429 		      0x0cc, BIT(9), 0);
434 				 0x0d0, 0, 3, 24, 2, BIT(31), 0);
437 		      0x100, BIT(0), 0);
439 		      0x100, BIT(1), 0);
441 		      0x100, BIT(3), 0);
443 		      0x100, BIT(5), 0);
445 		      0x100, BIT(25), 0);
447 		      0x100, BIT(26), 0);
449 		      0x100, BIT(29), 0);
451 		      0x100, BIT(31), 0);
456 				 0x104, 0, 4, 24, 2, BIT(31), 0);
459 				 0x10c, 0, 4, 24, 2, BIT(31), 0);
464 			       0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
468 				 0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
471 			     0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT);
475 static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
478 				       0x134, 0, 5, 24, 3, BIT(31), 0);
481 		      0x13c, BIT(31), CLK_SET_RATE_PARENT);
484 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
487 		      0x144, BIT(31), 0);
490 static const u8 hdmi_table[] = { 0, 2 };
493 				       0x150, 0, 4, 24, 2, BIT(31),
500 				 0x154, 0, 4, 24, 3, BIT(31), 0);
504 				  0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
507 		      0x160, BIT(31), 0);
735 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
736 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
738 	[RST_GPS]		=  { 0x0d0, BIT(30) },
740 	[RST_DE_BE]		=  { 0x104, BIT(30) },
742 	[RST_DE_FE]		=  { 0x10c, BIT(30) },
744 	[RST_TVE]		=  { 0x118, BIT(29) },
745 	[RST_LCD]		=  { 0x118, BIT(30) },
747 	[RST_CSI]		=  { 0x134, BIT(30) },
749 	[RST_VE]		=  { 0x13c, BIT(0) },
751 	[RST_GPU]		=  { 0x154, BIT(30) },
753 	[RST_IEP]		=  { 0x160, BIT(30) },
993 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));  in sun5i_ccu_init()
1002 	writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);  in sun5i_ccu_init()