clk/sunxi-ng/ccu-sun50i-h616.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
44 		.hw.init	= CLK_HW_INIT("pll-cpux", "osc24M",
60 		.hw.init	= CLK_HW_INIT("pll-ddr0", "osc24M",
75 		.hw.init	= CLK_HW_INIT("pll-ddr1", "osc24M",
92 		.hw.init	= CLK_HW_INIT("pll-periph0", "osc24M",
109 		.hw.init	= CLK_HW_INIT("pll-periph1", "osc24M",
124 		.hw.init	= CLK_HW_INIT("pll-gpu", "osc24M",
146 		.hw.init	= CLK_HW_INIT("pll-video0", "osc24M",
164 		.hw.init	= CLK_HW_INIT("pll-video1", "osc24M",
182 		.hw.init	= CLK_HW_INIT("pll-video2", "osc24M",
197 		.hw.init	= CLK_HW_INIT("pll-ve", "osc24M",
212 		.hw.init	= CLK_HW_INIT("pll-de", "osc24M",
233 		.hw.init	= CLK_HW_INIT("pll-audio-hs", "osc24M",
240 					"iosc", "pll-cpux", "pll-periph0" };
244 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
247 						      "iosc", "pll-periph0" };
248 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
257 						       "psi-ahb1-ahb2",
258 						       "pll-periph0" };
277 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
278 					     "pll-ddr0", "pll-ddr1" };
285 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
292 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
303 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
312 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
315 static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" };
321 static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674,
326 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
329 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
337 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
340 static const char * const ve_parents[] = { "pll-ve" };
347 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
350 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
353 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
358 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
361 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
364 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
366 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
368 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
381 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
383 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
385 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
387 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
389 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
391 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
394 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
397 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
398 					     "pll-periph1", "pll-periph0-2x",
399 					     "pll-periph1-2x" };
414 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
416 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
417 					    "pll-periph1-2x" };
423 					  2,		/* post-div */
431 					  2,		/* post-div */
439 					  2,		/* post-div */
442 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
443 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
444 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
446 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
447 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
448 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
449 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
450 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
451 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
453 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
454 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
455 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
456 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
457 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0);
473 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
474 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
476 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
479 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
480 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
482 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
490 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
492 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
494 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
496 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
497 					      "pll-audio-4x", "pll-audio-hs" };
511 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
526 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
528 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x",
534 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
541 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
550 		.hw.init	= CLK_HW_INIT_PARENTS("audio-hub",
557 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
568 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
569 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
571 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
572 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
574 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0);
575 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0);
577 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
578 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0);
580 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
581 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
582 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0);
583 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
584 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
585 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
586 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0);
587 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
588 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
590 static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0);
592 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x",
593 					     "pll-video2", "pll-video2-4x" };
600 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
602 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
622 		.hw.init	= CLK_HW_INIT_PARENTS("hdmi-cec",
629 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
631 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
634 static const char * const tcon_tv_parents[] = { "pll-video0",
635 						"pll-video0-4x",
636 						"pll-video1",
637 						"pll-video1-4x" };
638 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
645 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1",
653 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
655 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3",
666 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
668 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3",
671 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
672 static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
678 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
688  * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
689  * rates can be set exactly in conjunction with sigma-delta modulation.
691 static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
694 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
697 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
705 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
713 static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k",
720 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
724 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
727 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
730 static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x",
1118 	 * See the comment before pll-video0 definition for the reason.  in sun50i_h616_ccu_probe()
1139 	 * Force the post-divider of pll-audio to 12 and the output divider  in sun50i_h616_ccu_probe()
1155 	return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);  in sun50i_h616_ccu_probe()
1159 	{ .compatible = "allwinner,sun50i-h616-ccu" },
1167 		.name			= "sun50i-h616-ccu",