Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
37 .enable = BIT(31),
38 .lock = BIT(28),
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
51 .enable = BIT(31),
52 .lock = BIT(28),
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
66 .enable = BIT(31),
67 .lock = BIT(28),
75 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
83 .enable = BIT(31),
84 .lock = BIT(28),
92 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
101 .enable = BIT(31),
102 .lock = BIT(28),
107 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
119 .enable = BIT(31),
120 .lock = BIT(28),
129 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
137 .enable = BIT(31),
138 .lock = BIT(28),
147 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
155 .enable = BIT(31),
156 .lock = BIT(28),
162 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
170 .enable = BIT(31),
171 .lock = BIT(28),
177 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
185 .enable = BIT(31),
186 .lock = BIT(28),
192 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
209 { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
213 .enable = BIT(31),
214 .lock = BIT(28),
218 BIT(24), 0x178, BIT(31)),
222 .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
229 "iosc", "pll-cpux" };
231 0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
233 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
236 "iosc", "pll-periph0" };
237 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
242 24, 2, /* mux */
246 "psi-ahb1-ahb2",
247 "pll-periph0" };
251 24, 2, /* mux */
257 24, 2, /* mux */
263 24, 2, /* mux */
266 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
267 "pll-ddr0", "pll-periph0-4x" };
270 24, 2, /* mux */
271 BIT(31), /* gate */
274 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
277 24, 1, /* mux */
278 BIT(31), /* gate */
281 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
282 0x60c, BIT(0), 0);
284 static const char * const deinterlace_parents[] = { "pll-periph0",
285 "pll-periph1" };
290 24, 1, /* mux */
291 BIT(31), /* gate */
294 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
295 0x62c, BIT(0), 0);
298 static const char * const gpu_parents[] = { "pll-gpu" };
300 24, 1, /* mux */
301 BIT(31), /* gate */
304 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
305 0x67c, BIT(0), 0);
308 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
312 24, 1, /* mux */
313 BIT(31),/* gate */
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
317 0x68c, BIT(0), 0);
319 static const char * const ve_parents[] = { "pll-ve" };
322 24, 1, /* mux */
323 BIT(31), /* gate */
326 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
327 0x69c, BIT(0), 0);
332 24, 1, /* mux */
333 BIT(31),/* gate */
336 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
337 0x6bc, BIT(0), 0);
339 static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" };
342 24, 1, /* mux */
343 BIT(31), /* gate */
346 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
347 0x6cc, BIT(0), 0);
349 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
350 0x70c, BIT(0), 0);
352 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
353 0x71c, BIT(0), 0);
355 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
356 0x72c, BIT(0), 0);
358 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
359 0x73c, BIT(0), 0);
361 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
363 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
364 0x78c, BIT(0), 0);
366 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
367 0x79c, BIT(0), 0);
369 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
371 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
373 static const char * const dram_parents[] = { "pll-ddr0" };
376 .mux = _SUNXI_CCU_MUX(24, 2),
386 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
387 0x804, BIT(0), 0);
388 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
389 0x804, BIT(1), 0);
390 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
391 0x804, BIT(2), 0);
392 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
393 0x804, BIT(3), 0);
394 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
395 0x804, BIT(5), 0);
396 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
397 0x804, BIT(8), 0);
398 static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus",
399 0x804, BIT(11), 0);
401 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
402 0x80c, BIT(0), CLK_IS_CRITICAL);
404 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
405 "pll-periph1", "pll-periph0-2x",
406 "pll-periph1-2x" };
410 24, 3, /* mux */
411 BIT(31),/* gate */
417 24, 3, /* mux */
418 BIT(31),/* gate */
421 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
423 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
424 "pll-periph1-2x" };
428 24, 2, /* mux */
429 BIT(31), /* gate */
430 2, /* post-div */
436 24, 2, /* mux */
437 BIT(31), /* gate */
438 2, /* post-div */
444 24, 2, /* mux */
445 BIT(31), /* gate */
446 2, /* post-div */
449 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
450 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
451 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
453 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
454 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
455 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
456 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
458 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
459 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
460 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
461 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
463 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
464 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0);
469 24, 3, /* mux */
470 BIT(31),/* gate */
476 24, 3, /* mux */
477 BIT(31),/* gate */
480 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
481 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
483 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
485 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
489 24, 1, /* mux */
490 BIT(31),/* gate */
493 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
496 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0,
499 24, 1, /* mux */
500 BIT(31),/* gate */
503 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
505 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
507 static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" };
509 .enable = BIT(31),
511 .mux = _SUNXI_CCU_MUX(24, 2),
522 .enable = BIT(31),
524 .mux = _SUNXI_CCU_MUX(24, 2),
535 .enable = BIT(31),
537 .mux = _SUNXI_CCU_MUX(24, 2),
548 .enable = BIT(31),
550 .mux = _SUNXI_CCU_MUX(24, 2),
560 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0);
561 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0);
562 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0);
563 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0);
566 .enable = BIT(31),
568 .mux = _SUNXI_CCU_MUX(24, 2),
578 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
581 .enable = BIT(31),
583 .mux = _SUNXI_CCU_MUX(24, 2),
593 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
596 .enable = BIT(31),
598 .mux = _SUNXI_CCU_MUX(24, 2),
601 .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
608 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
617 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
618 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
620 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
622 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
623 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0);
624 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
625 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0);
627 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
628 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
629 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
630 static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
631 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
632 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
635 static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
636 &pll_periph0_4x_clk.hw, 24, 1, 0);
637 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
638 0xab0, BIT(31), 0);
639 static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
640 0xab0, BIT(30), 0);
642 static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi",
643 "pll-periph0", 0xab4,
645 BIT(31), /* gate */
648 static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8,
650 BIT(31), /* gate */
653 static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2",
654 0xabc, BIT(0), 0);
656 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1",
657 "pll-video1-4x" };
660 24, 2, /* mux */
661 BIT(31), /* gate */
664 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
666 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
673 .enable = BIT(31),
676 .shift = 24,
686 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
693 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
695 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
696 0xb5c, BIT(0), 0);
698 static const char * const tcon_lcd0_parents[] = { "pll-video0",
699 "pll-video0-4x",
700 "pll-video1" };
701 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
703 24, 3, /* mux */
704 BIT(31), /* gate */
707 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
708 0xb7c, BIT(0), 0);
710 static const char * const tcon_tv0_parents[] = { "pll-video0",
711 "pll-video0-4x",
712 "pll-video1",
713 "pll-video1-4x" };
714 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
718 24, 3, /* mux */
719 BIT(31), /* gate */
722 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
723 0xb9c, BIT(0), 0);
725 static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0);
727 static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
728 "pll-periph0" };
730 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
733 24, 3, /* mux */
734 BIT(31), /* gate */
737 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0",
738 "pll-periph0", "pll-periph1" };
739 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk",
742 24, 3, /* mux */
743 BIT(31), /* gate */
746 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
748 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
751 24, 2, /* mux */
752 BIT(31), /* gate */
755 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
765 * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
766 * rates can be set exactly in conjunction with sigma-delta modulation.
768 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
770 24, 1, CLK_SET_RATE_PARENT);
771 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
774 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
781 static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x",
784 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
791 static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x",
794 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
798 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
801 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
1080 [RST_MBUS] = { 0x540, BIT(30) },
1082 [RST_BUS_DE] = { 0x60c, BIT(16) },
1083 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
1084 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1085 [RST_BUS_CE] = { 0x68c, BIT(16) },
1086 [RST_BUS_VE] = { 0x69c, BIT(16) },
1087 [RST_BUS_EMCE] = { 0x6bc, BIT(16) },
1088 [RST_BUS_VP9] = { 0x6cc, BIT(16) },
1089 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1090 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1091 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1092 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1093 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1094 [RST_BUS_PSI] = { 0x79c, BIT(16) },
1095 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1096 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
1097 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1098 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1099 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1100 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1101 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1102 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1103 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1104 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1105 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1106 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1107 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1108 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1109 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1110 [RST_BUS_SCR0] = { 0x93c, BIT(16) },
1111 [RST_BUS_SCR1] = { 0x93c, BIT(17) },
1112 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1113 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1114 [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1115 [RST_BUS_TS] = { 0x9bc, BIT(16) },
1116 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1117 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1118 [RST_BUS_I2S0] = { 0xa1c, BIT(16) },
1119 [RST_BUS_I2S1] = { 0xa1c, BIT(17) },
1120 [RST_BUS_I2S2] = { 0xa1c, BIT(18) },
1121 [RST_BUS_I2S3] = { 0xa1c, BIT(19) },
1122 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1123 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1124 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
1126 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1127 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1128 [RST_USB_PHY3] = { 0xa7c, BIT(30) },
1129 [RST_USB_HSIC] = { 0xa7c, BIT(28) },
1131 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1132 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
1133 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1134 [RST_BUS_XHCI] = { 0xa8c, BIT(21) },
1135 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
1136 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1137 [RST_BUS_PCIE] = { 0xabc, BIT(16) },
1139 [RST_PCIE_POWERUP] = { 0xabc, BIT(17) },
1141 [RST_BUS_HDMI] = { 0xb1c, BIT(16) },
1142 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1143 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
1144 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1145 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1146 [RST_BUS_CSI] = { 0xc2c, BIT(16) },
1147 [RST_BUS_HDCP] = { 0xc4c, BIT(16) },
1188 .bypass_index = 0, /* index of 24 MHz oscillator */
1206 val &= ~(GENMASK(15, 8) | BIT(0)); in sun50i_h6_ccu_probe()
1218 val |= BIT(29); in sun50i_h6_ccu_probe()
1225 * See the comment before pll-video0 definition for the reason. in sun50i_h6_ccu_probe()
1229 val &= ~BIT(0); in sun50i_h6_ccu_probe()
1241 val &= ~GENMASK(25, 24); in sun50i_h6_ccu_probe()
1246 * Force the post-divider of pll-audio to 12 and the output divider in sun50i_h6_ccu_probe()
1250 val &= ~(GENMASK(21, 16) | BIT(0)); in sun50i_h6_ccu_probe()
1251 writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG); in sun50i_h6_ccu_probe()
1259 val |= BIT(24); in sun50i_h6_ccu_probe()
1262 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); in sun50i_h6_ccu_probe()
1274 { .compatible = "allwinner,sun50i-h6-ccu" },
1282 .name = "sun50i-h6-ccu",