clk/sunxi-ng/ccu-sun50i-a100.c

39  * The M factor is present in the register's description, but not in the
40  * frequency formula, and it's documented as "M is only used for backdoor
47 	.mult		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
61 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
62 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
77 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
78 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
94 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
95 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
112 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
113 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
131 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
132 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
147 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
148 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
163 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
164 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
179 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
180 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
191  * The COM PLL has m0 dividers in addition to the usual N, M
197 	{ .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },
203 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
204 	.m		= _SUNXI_CCU_DIV(0, 1),
220 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
221 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
233  * The Audio PLL has m0, m1 dividers in addition to the usual N, M
240 	{ .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
241 	{ .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
242 	{ .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
243 	{ .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
249 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
250 	.m		= _SUNXI_CCU_DIV(16, 6),
270 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
277 			     0, 2,	/* M */
278 			     8, 2,	/* P */
287 			     0, 2,	/* M */
288 			     8, 2,	/* P */
293 			     0, 2,	/* M */
294 			     8, 2,	/* P */
299 			     0, 2,	/* M */
300 			     8, 2,	/* P */
308 				 0, 3,		/* M */
315 				 0, 4,		/* M */
329 				 0, 4,		/* M */
339 				       0, 2,	/* M */
349 				  0, 4,		/* M */
350 				  8, 2,		/* P */
360 				 0, 3,		/* M */
401 		      0x804, BIT(8), 0);
416 				  0, 4,		/* M */
417 				  8, 2,		/* P */
423 				  0, 4,		/* M */
424 				  8, 2,		/* P */
434 					  0, 4,		/* M */
435 					  8, 2,		/* P */
442 					  0, 4,		/* M */
443 					  8, 2,		/* P */
450 					  0, 4,		/* M */
451 					  8, 2,		/* P */
473 				  0, 4,		/* M */
474 				  8, 2,		/* P */
480 				  0, 4,		/* M */
481 				  8, 2,		/* P */
487 				  0, 4,		/* M */
488 				  8, 2,		/* P */
497 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
505 				  0, 4,		/* M */
506 				  8, 2,		/* P */
514 				  0, 4,		/* M */
515 				  8, 2,		/* P */
529 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
542 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
555 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
568 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
586 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
601 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
616 				 0, 4,		/* M */
623 				 0, 4,		/* M */
630 				 0, 4,		/* M */
639  * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
640  * We will force them to 0 (12M divided from 48M).
655 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
670 				 0, 4,		/* M */
685 				  0, 4,		/* M */
686 				  8, 2,		/* P */
698 				  0, 4,		/* M */
699 				  8, 2,		/* P */
713 				 0, 4,		/* M */
723 				 0, 5,		/* M */
733 				 0, 5,		/* M */
747 				 0, 5,		/* M */
1238 	 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)  in sun50i_a100_ccu_probe()