1 // SPDX-License-Identifier: GPL-2.0
3  * StarFive JH7110 Video-Output Clock Driver
5  * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/starfive,jh7110-crg.h>
17 #include "clk-starfive-jh7110.h"
76 	top_rst = devm_reset_control_get_shared(priv->dev, NULL);  in jh7110_vout_top_rst_init()
78 		return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");  in jh7110_vout_top_rst_init()
86 	unsigned int idx = clkspec->args[0];  in jh7110_voutclk_get()
89 		return &priv->reg[idx].hw;  in jh7110_voutclk_get()
91 	return ERR_PTR(-EINVAL);  in jh7110_voutclk_get()
99 	clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);  in jh7110_voutcrg_suspend()
108 	return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);  in jh7110_voutcrg_resume()
123 	priv = devm_kzalloc(&pdev->dev,  in jh7110_voutcrg_probe()
127 		return -ENOMEM;  in jh7110_voutcrg_probe()
129 	top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);  in jh7110_voutcrg_probe()
131 		return -ENOMEM;  in jh7110_voutcrg_probe()
133 	spin_lock_init(&priv->rmw_lock);  in jh7110_voutcrg_probe()
134 	priv->dev = &pdev->dev;  in jh7110_voutcrg_probe()
135 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in jh7110_voutcrg_probe()
136 	if (IS_ERR(priv->base))  in jh7110_voutcrg_probe()
137 		return PTR_ERR(priv->base);  in jh7110_voutcrg_probe()
139 	top->top_clks = jh7110_vout_top_clks;  in jh7110_voutcrg_probe()
140 	top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);  in jh7110_voutcrg_probe()
141 	ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);  in jh7110_voutcrg_probe()
143 		return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");  in jh7110_voutcrg_probe()
144 	dev_set_drvdata(priv->dev, top);  in jh7110_voutcrg_probe()
147 	pm_runtime_enable(priv->dev);  in jh7110_voutcrg_probe()
148 	ret = pm_runtime_resume_and_get(priv->dev);  in jh7110_voutcrg_probe()
150 		return dev_err_probe(priv->dev, ret, "failed to turn on power\n");  in jh7110_voutcrg_probe()
167 		struct jh71x0_clk *clk = &priv->reg[idx];  in jh7110_voutcrg_probe()
169 		const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {  in jh7110_voutcrg_probe()
182 				parents[i].hw = &priv->reg[pidx].hw;  in jh7110_voutcrg_probe()
184 				parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];  in jh7110_voutcrg_probe()
187 		clk->hw.init = &init;  in jh7110_voutcrg_probe()
188 		clk->idx = idx;  in jh7110_voutcrg_probe()
189 		clk->max_div = max & JH71X0_CLK_DIV_MASK;  in jh7110_voutcrg_probe()
191 		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);  in jh7110_voutcrg_probe()
196 	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);  in jh7110_voutcrg_probe()
200 	ret = jh7110_reset_controller_register(priv, "rst-vo", 4);  in jh7110_voutcrg_probe()
207 	pm_runtime_put_sync(priv->dev);  in jh7110_voutcrg_probe()
208 	pm_runtime_disable(priv->dev);  in jh7110_voutcrg_probe()
214 	pm_runtime_put_sync(&pdev->dev);  in jh7110_voutcrg_remove()
215 	pm_runtime_disable(&pdev->dev);  in jh7110_voutcrg_remove()
219 	{ .compatible = "starfive,jh7110-voutcrg" },
228 		.name = "clk-starfive-jh7110-vout",
236 MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");