1 // SPDX-License-Identifier: GPL-2.0
3  * StarFive JH7110 System Clock Driver
11 #include <linux/clk-provider.h>
17 #include <soc/starfive/reset-starfive-jh71x0.h>
19 #include <dt-bindings/clock/starfive,jh7110-crg.h>
21 #include "clk-starfive-jh7110.h"
329 	unsigned int idx = clkspec->args[0];  in jh7110_sysclk_get()
332 		return &priv->reg[idx].hw;  in jh7110_sysclk_get()
334 	return ERR_PTR(-EINVAL);  in jh7110_sysclk_get()
363 		return -ENOMEM;  in jh7110_reset_controller_register()
365 	rdev->base = priv->base;  in jh7110_reset_controller_register()
367 	adev = &rdev->adev;  in jh7110_reset_controller_register()
368 	adev->name = adev_name;  in jh7110_reset_controller_register()
369 	adev->dev.parent = priv->dev;  in jh7110_reset_controller_register()
370 	adev->dev.release = jh7110_reset_adev_release;  in jh7110_reset_controller_register()
371 	adev->id = adev_id;  in jh7110_reset_controller_register()
383 	return devm_add_action_or_reset(priv->dev,  in jh7110_reset_controller_register()
398 	struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;  in jh7110_pll0_clk_notifier_cb()
402 		struct clk *osc = clk_get(priv->dev, "osc");  in jh7110_pll0_clk_notifier_cb()
404 		priv->original_clk = clk_get_parent(cpu_root);  in jh7110_pll0_clk_notifier_cb()
408 		ret = clk_set_parent(cpu_root, priv->original_clk);  in jh7110_pll0_clk_notifier_cb()
421 	priv = devm_kzalloc(&pdev->dev,  in jh7110_syscrg_probe()
425 		return -ENOMEM;  in jh7110_syscrg_probe()
427 	spin_lock_init(&priv->rmw_lock);  in jh7110_syscrg_probe()
428 	priv->dev = &pdev->dev;  in jh7110_syscrg_probe()
429 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in jh7110_syscrg_probe()
430 	if (IS_ERR(priv->base))  in jh7110_syscrg_probe()
431 		return PTR_ERR(priv->base);  in jh7110_syscrg_probe()
434 	pllclk = clk_get(priv->dev, "pll0_out");  in jh7110_syscrg_probe()
436 		/* 24MHz -> 1000.0MHz */  in jh7110_syscrg_probe()
437 		priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",  in jh7110_syscrg_probe()
439 		if (IS_ERR(priv->pll[0]))  in jh7110_syscrg_probe()
440 			return PTR_ERR(priv->pll[0]);  in jh7110_syscrg_probe()
442 		priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;  in jh7110_syscrg_probe()
443 		ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);  in jh7110_syscrg_probe()
446 		priv->pll[0] = NULL;  in jh7110_syscrg_probe()
449 	pllclk = clk_get(priv->dev, "pll1_out");  in jh7110_syscrg_probe()
451 		/* 24MHz -> 1066.0MHz */  in jh7110_syscrg_probe()
452 		priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",  in jh7110_syscrg_probe()
454 		if (IS_ERR(priv->pll[1]))  in jh7110_syscrg_probe()
455 			return PTR_ERR(priv->pll[1]);  in jh7110_syscrg_probe()
458 		priv->pll[1] = NULL;  in jh7110_syscrg_probe()
461 	pllclk = clk_get(priv->dev, "pll2_out");  in jh7110_syscrg_probe()
463 		/* 24MHz -> 1188.0MHz */  in jh7110_syscrg_probe()
464 		priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",  in jh7110_syscrg_probe()
466 		if (IS_ERR(priv->pll[2]))  in jh7110_syscrg_probe()
467 			return PTR_ERR(priv->pll[2]);  in jh7110_syscrg_probe()
470 		priv->pll[2] = NULL;  in jh7110_syscrg_probe()
484 		struct jh71x0_clk *clk = &priv->reg[idx];  in jh7110_syscrg_probe()
491 				parents[i].hw = &priv->reg[pidx].hw;  in jh7110_syscrg_probe()
510 			else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0])  in jh7110_syscrg_probe()
512 			else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1])  in jh7110_syscrg_probe()
514 			else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2])  in jh7110_syscrg_probe()
517 				parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];  in jh7110_syscrg_probe()
520 		clk->hw.init = &init;  in jh7110_syscrg_probe()
521 		clk->idx = idx;  in jh7110_syscrg_probe()
522 		clk->max_div = max & JH71X0_CLK_DIV_MASK;  in jh7110_syscrg_probe()
524 		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);  in jh7110_syscrg_probe()
529 	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);  in jh7110_syscrg_probe()
533 	return jh7110_reset_controller_register(priv, "rst-sys", 0);  in jh7110_syscrg_probe()
537 	{ .compatible = "starfive,jh7110-syscrg" },
543 		.name = "clk-starfive-jh7110-sys",