Lines Matching +full:ch3 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
26 #define PLL_BW_GOODREF (0L)
88 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
89 CLKGEN_FIELD(0x2f0, 0x1, 1),
90 CLKGEN_FIELD(0x2f0, 0x1, 2),
91 CLKGEN_FIELD(0x2f0, 0x1, 3) },
92 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
93 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
94 CLKGEN_FIELD(0x2f0, 0x1, 9),
95 CLKGEN_FIELD(0x2f0, 0x1, 10),
96 CLKGEN_FIELD(0x2f0, 0x1, 11) },
98 .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
99 CLKGEN_FIELD(0x308, 0x1, 24),
100 CLKGEN_FIELD(0x30c, 0x1, 24),
101 CLKGEN_FIELD(0x310, 0x1, 24) },
102 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
103 CLKGEN_FIELD(0x308, 0x1f, 15),
104 CLKGEN_FIELD(0x30c, 0x1f, 15),
105 CLKGEN_FIELD(0x310, 0x1f, 15) },
106 .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
107 CLKGEN_FIELD(0x2fc, 0x1, 1),
108 CLKGEN_FIELD(0x2fc, 0x1, 2),
109 CLKGEN_FIELD(0x2fc, 0x1, 3) },
110 .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
111 .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
112 CLKGEN_FIELD(0x308, 0x7fff, 0),
113 CLKGEN_FIELD(0x30c, 0x7fff, 0),
114 CLKGEN_FIELD(0x310, 0x7fff, 0) },
115 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
116 CLKGEN_FIELD(0x308, 0xf, 20),
117 CLKGEN_FIELD(0x30c, 0xf, 20),
118 CLKGEN_FIELD(0x310, 0xf, 20) },
120 .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
142 .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
143 CLKGEN_FIELD(0x2a0, 0x1, 1),
144 CLKGEN_FIELD(0x2a0, 0x1, 2),
145 CLKGEN_FIELD(0x2a0, 0x1, 3) },
146 .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16),
147 .pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
148 CLKGEN_FIELD(0x2b8, 0x7fff, 0),
149 CLKGEN_FIELD(0x2bc, 0x7fff, 0),
150 CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
151 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
152 CLKGEN_FIELD(0x2b8, 0xf, 20),
153 CLKGEN_FIELD(0x2bc, 0xf, 20),
154 CLKGEN_FIELD(0x2c0, 0xf, 20) },
155 .npda = CLKGEN_FIELD(0x2a0, 0x1, 12),
156 .nsb = { CLKGEN_FIELD(0x2a0, 0x1, 8),
157 CLKGEN_FIELD(0x2a0, 0x1, 9),
158 CLKGEN_FIELD(0x2a0, 0x1, 10),
159 CLKGEN_FIELD(0x2a0, 0x1, 11) },
161 .nsdiv = { CLKGEN_FIELD(0x2b4, 0x1, 24),
162 CLKGEN_FIELD(0x2b8, 0x1, 24),
163 CLKGEN_FIELD(0x2bc, 0x1, 24),
164 CLKGEN_FIELD(0x2c0, 0x1, 24) },
165 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
166 CLKGEN_FIELD(0x2b8, 0x1f, 15),
167 CLKGEN_FIELD(0x2bc, 0x1f, 15),
168 CLKGEN_FIELD(0x2c0, 0x1f, 15) },
169 .en = { CLKGEN_FIELD(0x2ac, 0x1, 0),
170 CLKGEN_FIELD(0x2ac, 0x1, 1),
171 CLKGEN_FIELD(0x2ac, 0x1, 2),
172 CLKGEN_FIELD(0x2ac, 0x1, 3) },
174 .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
188 { .name = "clk-s-d0-fs0-ch2", },
189 { .name = "clk-s-d0-fs0-ch3", },
198 { .name = "clk-s-d2-fs0-ch0", },
199 { .name = "clk-s-d2-fs0-ch1", },
200 { .name = "clk-s-d2-fs0-ch2", },
201 { .name = "clk-s-d2-fs0-ch3", },
210 { .name = "clk-s-d3-fs0-ch0", },
211 { .name = "clk-s-d3-fs0-ch1", },
212 { .name = "clk-s-d3-fs0-ch2", },
213 { .name = "clk-s-d3-fs0-ch3", },
225 * prepare - clk_(un)prepare only ensures parent is (un)prepared
226 * enable - clk_enable and clk_disable are functional & control the Fsyn
227 * rate - inherits rate from parent. set_rate/round_rate/recalc_rate
228 * parent - fixed parent. No clk_set_parent support
232 * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of
236 * @hw: handle between common and hardware-specific interfaces.
255 unsigned long flags = 0, timeout = jiffies + msecs_to_jiffies(10); in quadfs_pll_enable()
257 if (pll->lock) in quadfs_pll_enable()
258 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_enable()
263 if (pll->data->reset_present) in quadfs_pll_enable()
269 if (pll->data->bwfilter_present) in quadfs_pll_enable()
273 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_enable()
278 CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity); in quadfs_pll_enable()
280 if (pll->lock) in quadfs_pll_enable()
281 spin_unlock_irqrestore(pll->lock, flags); in quadfs_pll_enable()
283 if (pll->data->lockstatus_present) in quadfs_pll_enable()
286 return -ETIMEDOUT; in quadfs_pll_enable()
290 return 0; in quadfs_pll_enable()
296 unsigned long flags = 0; in quadfs_pll_disable()
298 if (pll->lock) in quadfs_pll_disable()
299 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_disable()
305 CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity); in quadfs_pll_disable()
307 if (pll->data->reset_present) in quadfs_pll_disable()
308 CLKGEN_WRITE(pll, nreset, 0); in quadfs_pll_disable()
310 if (pll->lock) in quadfs_pll_disable()
311 spin_unlock_irqrestore(pll->lock, flags); in quadfs_pll_disable()
319 return pll->data->powerup_polarity ? !npda : !!npda; in quadfs_pll_is_enabled()
325 unsigned long nd = fs->ndiv + 16; /* ndiv value */ in clk_fs660c32_vco_get_rate()
329 return 0; in clk_fs660c32_vco_get_rate()
336 unsigned long rate = 0; in quadfs_pll_fs660c32_recalc_rate()
344 pll->ndiv = params.ndiv; in quadfs_pll_fs660c32_recalc_rate()
360 return -EINVAL; in clk_fs660c32_vco_get_params()
365 return -EINVAL; in clk_fs660c32_vco_get_params()
373 fs->ndiv = n - 16; /* Converting formula value to reg value */ in clk_fs660c32_vco_get_params()
375 return 0; in clk_fs660c32_vco_get_params()
401 long hwrate = 0; in quadfs_pll_fs660c32_set_rate()
402 unsigned long flags = 0; in quadfs_pll_fs660c32_set_rate()
406 return -EINVAL; in quadfs_pll_fs660c32_set_rate()
414 pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n", in quadfs_pll_fs660c32_set_rate()
419 return -EINVAL; in quadfs_pll_fs660c32_set_rate()
421 pll->ndiv = params.ndiv; in quadfs_pll_fs660c32_set_rate()
423 if (pll->lock) in quadfs_pll_fs660c32_set_rate()
424 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_fs660c32_set_rate()
426 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_fs660c32_set_rate()
428 if (pll->lock) in quadfs_pll_fs660c32_set_rate()
429 spin_unlock_irqrestore(pll->lock, flags); in quadfs_pll_fs660c32_set_rate()
431 return 0; in quadfs_pll_fs660c32_set_rate()
456 return ERR_PTR(-EINVAL); in st_clk_register_quadfs_pll()
460 return ERR_PTR(-ENOMEM); in st_clk_register_quadfs_pll()
463 init.ops = quadfs->pll_ops; in st_clk_register_quadfs_pll()
468 pll->data = quadfs; in st_clk_register_quadfs_pll()
469 pll->regs_base = reg; in st_clk_register_quadfs_pll()
470 pll->lock = lock; in st_clk_register_quadfs_pll()
471 pll->hw.init = &init; in st_clk_register_quadfs_pll()
473 clk = clk_register(NULL, &pll->hw); in st_clk_register_quadfs_pll()
485 * prepare - clk_(un)prepare only ensures parent is (un)prepared
486 * enable - clk_enable and clk_disable are functional
487 * rate - set rate is functional
488 * parent - fixed parent. No clk_set_parent support
492 * struct st_clk_quadfs_fsynth - One clock output from a four channel digital
495 * @hw: handle between common and hardware-specific interfaces
539 CLKGEN_WRITE(fs, en[fs->chan], 1); in quadfs_fsynth_program_enable()
540 CLKGEN_WRITE(fs, en[fs->chan], 0); in quadfs_fsynth_program_enable()
545 unsigned long flags = 0; in quadfs_fsynth_program_rate()
552 CLKGEN_WRITE(fs, en[fs->chan], 0); in quadfs_fsynth_program_rate()
554 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
555 CLKGEN_WRITE(fs, pe[fs->chan], fs->pe); in quadfs_fsynth_program_rate()
556 CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv); in quadfs_fsynth_program_rate()
558 if (fs->lock) in quadfs_fsynth_program_rate()
559 spin_lock_irqsave(fs->lock, flags); in quadfs_fsynth_program_rate()
561 if (fs->data->nsdiv_present) in quadfs_fsynth_program_rate()
562 CLKGEN_WRITE(fs, nsdiv[fs->chan], fs->nsdiv); in quadfs_fsynth_program_rate()
564 if (fs->lock) in quadfs_fsynth_program_rate()
565 spin_unlock_irqrestore(fs->lock, flags); in quadfs_fsynth_program_rate()
571 unsigned long flags = 0; in quadfs_fsynth_enable()
577 if (fs->lock) in quadfs_fsynth_enable()
578 spin_lock_irqsave(fs->lock, flags); in quadfs_fsynth_enable()
580 CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity); in quadfs_fsynth_enable()
582 if (fs->data->nrst_present) in quadfs_fsynth_enable()
583 CLKGEN_WRITE(fs, nrst[fs->chan], 0); in quadfs_fsynth_enable()
585 if (fs->lock) in quadfs_fsynth_enable()
586 spin_unlock_irqrestore(fs->lock, flags); in quadfs_fsynth_enable()
590 return 0; in quadfs_fsynth_enable()
596 unsigned long flags = 0; in quadfs_fsynth_disable()
600 if (fs->lock) in quadfs_fsynth_disable()
601 spin_lock_irqsave(fs->lock, flags); in quadfs_fsynth_disable()
603 CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity); in quadfs_fsynth_disable()
605 if (fs->lock) in quadfs_fsynth_disable()
606 spin_unlock_irqrestore(fs->lock, flags); in quadfs_fsynth_disable()
612 u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]); in quadfs_fsynth_is_enabled()
614 pr_debug("%s: %s enable bit = 0x%x\n", in quadfs_fsynth_is_enabled()
617 return fs->data->standby_polarity ? !nsb : !!nsb; in quadfs_fsynth_is_enabled()
625 unsigned long s = (1 << fs->sdiv); in clk_fs660c32_dig_get_rate()
634 * 0 3 in clk_fs660c32_dig_get_rate()
637 ns = (fs->nsdiv == 1) ? 1 : 3; in clk_fs660c32_dig_get_rate()
639 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
642 return 0; in clk_fs660c32_dig_get_rate()
656 *p = (uint64_t)input * P20 - (32LL + (uint64_t)m) * val * (P20 / 32LL); in clk_fs660c32_get_pe()
670 new_deviation = abs(output - new_freq); in clk_fs660c32_get_pe()
673 fs->mdiv = m; in clk_fs660c32_get_pe()
674 fs->pe = (unsigned long)*p; in clk_fs660c32_get_pe()
675 fs->sdiv = si; in clk_fs660c32_get_pe()
676 fs->nsdiv = 1; in clk_fs660c32_get_pe()
679 return 0; in clk_fs660c32_get_pe()
685 int si; /* sdiv_reg (8 downto 0) */ in clk_fs660c32_dig_get_params()
689 unsigned long deviation = ~0; in clk_fs660c32_dig_get_params()
695 for (si = 0; (si <= 8) && deviation; si++) { in clk_fs660c32_dig_get_params()
698 r1 = clk_fs660c32_get_pe(0, si, &deviation, in clk_fs660c32_dig_get_params()
714 if (deviation == ~0) /* No solution found */ in clk_fs660c32_dig_get_params()
715 return -1; in clk_fs660c32_dig_get_params()
717 /* pe fine tuning if deviation not 0: +/- 2 around computed pe value */ in clk_fs660c32_dig_get_params()
719 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
720 fs_tmp.sdiv = fs->sdiv; in clk_fs660c32_dig_get_params()
721 fs_tmp.nsdiv = fs->nsdiv; in clk_fs660c32_dig_get_params()
723 if (fs->pe > 2) in clk_fs660c32_dig_get_params()
724 p2 = fs->pe - 2; in clk_fs660c32_dig_get_params()
726 p2 = 0; in clk_fs660c32_dig_get_params()
728 for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) { in clk_fs660c32_dig_get_params()
733 new_deviation = abs(output - new_freq); in clk_fs660c32_dig_get_params()
737 fs->pe = (unsigned long)p2; in clk_fs660c32_dig_get_params()
743 return 0; in clk_fs660c32_dig_get_params()
752 params->mdiv = CLKGEN_READ(fs, mdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
753 params->pe = CLKGEN_READ(fs, pe[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
754 params->sdiv = CLKGEN_READ(fs, sdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
756 if (fs->data->nsdiv_present) in quadfs_fsynt_get_hw_value_for_recalc()
757 params->nsdiv = CLKGEN_READ(fs, nsdiv[fs->chan]); in quadfs_fsynt_get_hw_value_for_recalc()
759 params->nsdiv = 1; in quadfs_fsynt_get_hw_value_for_recalc()
764 if (!params->mdiv && !params->pe && !params->sdiv) in quadfs_fsynt_get_hw_value_for_recalc()
767 fs->md = params->mdiv; in quadfs_fsynt_get_hw_value_for_recalc()
768 fs->pe = params->pe; in quadfs_fsynt_get_hw_value_for_recalc()
769 fs->sdiv = params->sdiv; in quadfs_fsynt_get_hw_value_for_recalc()
770 fs->nsdiv = params->nsdiv; in quadfs_fsynt_get_hw_value_for_recalc()
772 return 0; in quadfs_fsynt_get_hw_value_for_recalc()
782 unsigned long rate = 0; in quadfs_find_best_rate()
784 clk_fs_get_rate = fs->data->get_rate; in quadfs_find_best_rate()
785 clk_fs_get_params = fs->data->get_params; in quadfs_find_best_rate()
797 unsigned long rate = 0; in quadfs_recalc_rate()
802 clk_fs_get_rate = fs->data->get_rate; in quadfs_recalc_rate()
805 return 0; in quadfs_recalc_rate()
824 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", in quadfs_round_rate()
836 fs->md = params->mdiv; in quadfs_program_and_enable()
837 fs->pe = params->pe; in quadfs_program_and_enable()
838 fs->sdiv = params->sdiv; in quadfs_program_and_enable()
839 fs->nsdiv = params->nsdiv; in quadfs_program_and_enable()
857 return -EINVAL; in quadfs_set_rate()
859 memset(¶ms, 0, sizeof(struct stm_fs)); in quadfs_set_rate()
863 return -EINVAL; in quadfs_set_rate()
867 return 0; in quadfs_set_rate()
894 return ERR_PTR(-EINVAL); in st_clk_register_quadfs_fsynth()
898 return ERR_PTR(-ENOMEM); in st_clk_register_quadfs_fsynth()
906 fs->data = quadfs; in st_clk_register_quadfs_fsynth()
907 fs->regs_base = reg; in st_clk_register_quadfs_fsynth()
908 fs->chan = chan; in st_clk_register_quadfs_fsynth()
909 fs->lock = lock; in st_clk_register_quadfs_fsynth()
910 fs->hw.init = &init; in st_clk_register_quadfs_fsynth()
912 clk = clk_register(NULL, &fs->hw); in st_clk_register_quadfs_fsynth()
932 clk_data->clk_num = QUADFS_MAX_CHAN; in st_of_create_quadfs_fsynths()
933 clk_data->clks = kcalloc(QUADFS_MAX_CHAN, sizeof(struct clk *), in st_of_create_quadfs_fsynths()
936 if (!clk_data->clks) { in st_of_create_quadfs_fsynths()
941 for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { in st_of_create_quadfs_fsynths()
944 unsigned long flags = 0; in st_of_create_quadfs_fsynths()
946 if (quadfs->outputs) { in st_of_create_quadfs_fsynths()
947 clk_name = quadfs->outputs[fschan].name; in st_of_create_quadfs_fsynths()
948 flags = quadfs->outputs[fschan].flags; in st_of_create_quadfs_fsynths()
951 "clock-output-names", in st_of_create_quadfs_fsynths()
960 if (*clk_name == '\0') in st_of_create_quadfs_fsynths()
964 quadfs->data, reg, fschan, in st_of_create_quadfs_fsynths()
972 clk_data->clks[fschan] = clk; in st_of_create_quadfs_fsynths()
996 reg = of_iomap(np, 0); in st_of_quadfs_setup()
999 reg = of_iomap(parent_np, 0); in st_of_quadfs_setup()
1007 clk_parent_name = of_clk_get_parent_name(np, 0); in st_of_quadfs_setup()
1021 clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, datac->data, in st_of_quadfs_setup()
1043 CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);
1057 CLK_OF_DECLARE(quadfs660D0, "st,quadfs-d0", st_of_quadfs660D0_setup);
1064 CLK_OF_DECLARE(quadfs660D2, "st,quadfs-d2", st_of_quadfs660D2_setup);
1071 CLK_OF_DECLARE(quadfs660D3, "st,quadfs-d3", st_of_quadfs660D3_setup);