Lines Matching refs:RAS_CLK_ENB
69 #define RAS_CLK_ENB (misc_base + 0x034) macro
610 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, in spear3xx_clk_init()
614 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, in spear3xx_clk_init()
620 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); in spear3xx_clk_init()
624 RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock); in spear3xx_clk_init()
628 RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock); in spear3xx_clk_init()
632 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); in spear3xx_clk_init()
636 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); in spear3xx_clk_init()
640 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, in spear3xx_clk_init()
645 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, in spear3xx_clk_init()
650 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, in spear3xx_clk_init()
655 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, in spear3xx_clk_init()