Lines Matching +full:2 +full:c400000
23 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
25 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
27 #define SPEAR1310_PLL_CLK_MASK 2
51 #define SPEAR1310_UART_CLK_SYNT_VAL 2
52 #define SPEAR1310_UART_CLK_MASK 2
57 #define SPEAR1310_CLCD_CLK_MASK 2
58 #define SPEAR1310_CLCD_CLK_SHIFT 2
67 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
84 #define SPEAR1310_I2S_REF_SHIFT 2
85 #define SPEAR1310_I2S_SRC_CLK_MASK 2
131 #define SPEAR1310_SYSRAM1_CLK_ENB 2
143 #define SPEAR1310_CPU_DBG_CLK_ENB 2
164 #define SPEAR1310_OSC_24M_CLK_ENB 2
197 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
223 #define SPEAR1310_MII1_CLK_ENB 2
254 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
255 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
257 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
264 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
266 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
325 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
340 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
459 2); in spear1310_clk_init()
467 2); in spear1310_clk_init()
471 2); in spear1310_clk_init()
489 CLK_SET_RATE_PARENT, 1, 2); in spear1310_clk_init()
493 2); in spear1310_clk_init()
497 2); in spear1310_clk_init()
911 clk_register_clkdev(clk, NULL, "5c400000.eth"); in spear1310_clk_init()
935 clk_register_clkdev(clk, "stmmacphy.2", NULL); in spear1310_clk_init()