clk/spear/spear1310_clock.c

109 	#define SPEAR1310_DMA_CLK_ENB			25
200 	#define SPEAR1310_CAN1_CLK_ENB			25
231 	/* PCLK 24MHz */
232 	{.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 	{.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
237 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
243 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
244 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
245 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
251 	/* For VCO1div2 = 500 MHz */
252 	{.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
253 	{.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
254 	{.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
255 	{.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
256 	{.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
257 	{.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
271 	{.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
272 	{.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
273 	{.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
274 	{.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
275 	{.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
276 	{.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
277 	{.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
278 	{.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
279 	{.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
280 	{.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
310 	/* For parent clk = 49.152 MHz */
311 	{.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
312 	{.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
313 	{.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
314 	{.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
317 	 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
318 	 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
322 	/* For parent clk = 49.152 MHz */
323 	{.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
325 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
330 	/* For i2s_ref_clk = 12.288MHz */
331 	{.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
332 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
336 /* possible adc range is 2.5 MHz to 20 MHz. */
338 	/* For ahb = 166.67 MHz */
339 	{.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
340 	{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
341 	{.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
342 	{.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
347 	/* For vco1div4 = 250 MHz */
348 	{.div = 0x14000}, /* 25 MHz */
349 	{.div = 0x0A000}, /* 50 MHz */
350 	{.div = 0x05000}, /* 100 MHz */
351 	{.div = 0x02000}, /* 250 MHz */
408 	/* clock derived from 24 or 25 MHz osc clk */  in spear1310_clk_init()