Lines Matching refs:div_sel
22 unsigned long div_sel, in ipll_calc_rate() argument
27 rate *= div_sel; in ipll_calc_rate()
53 unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; in ipll_find_rate() local
69 div_sel = div; in ipll_find_rate()
79 detected = PLL_SET_DIV_SEL(detected, div_sel); in ipll_find_rate()
97 static void pll_get_mode_ctrl(unsigned long div_sel, in pll_get_mode_ctrl() argument
109 if (mode_ctrl_check(div_sel, ictrl, mode)) { in pll_get_mode_ctrl()
119 static bool ipll_check_mode_ctrl_restrict(unsigned long div_sel, in ipll_check_mode_ctrl_restrict() argument
123 unsigned long left_rest = 20 * div_sel; in ipll_check_mode_ctrl_restrict()
124 unsigned long right_rest = 35 * div_sel; in ipll_check_mode_ctrl_restrict()
198 unsigned long div_sel, in fpll_calc_rate() argument
203 u64 dividend = parent_rate * div_sel; in fpll_calc_rate()
289 unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; in fpll_find_rate() local
308 div_sel = div; in fpll_find_rate()
318 detected = PLL_SET_DIV_SEL(detected, div_sel); in fpll_find_rate()
341 static bool fpll_check_mode_ctrl_restrict(unsigned long div_sel, in fpll_check_mode_ctrl_restrict() argument
345 unsigned long left_rest = 10 * div_sel; in fpll_check_mode_ctrl_restrict()
346 unsigned long right_rest = 24 * div_sel; in fpll_check_mode_ctrl_restrict()