605 static u8 mmux_get_parent_id(struct cv1800_clk_mmux *mmux)  in mmux_get_parent_id()  argument
607 	struct clk_hw *hw = &mmux->common.hw;  in mmux_get_parent_id()
621 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_enable()  local
623 	return cv1800_clk_setbit(&mmux->common, &mmux->gate);  in mmux_enable()
628 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_disable()  local
630 	cv1800_clk_clearbit(&mmux->common, &mmux->gate);  in mmux_disable()
635 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_is_enabled()  local
637 	return cv1800_clk_checkbit(&mmux->common, &mmux->gate);  in mmux_is_enabled()
643 	struct cv1800_clk_mmux *mmux = data;  in mmux_round_rate()  local
647 		if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))  in mmux_round_rate()
650 		id = mmux_get_parent_id(mmux);  in mmux_round_rate()
653 	div_id = mmux->parent2sel[id];  in mmux_round_rate()
658 	return div_helper_round_rate(&mmux->div[div_id],  in mmux_round_rate()
659 				     &mmux->common.hw, parent,  in mmux_round_rate()
666 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_determine_rate()  local
668 	return mux_helper_determine_rate(&mmux->common, req,  in mmux_determine_rate()
669 					 mmux_round_rate, mmux);  in mmux_determine_rate()
675 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_recalc_rate()  local
679 	if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))  in mmux_recalc_rate()
682 	if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))  in mmux_recalc_rate()
683 		div = &mmux->div[0];  in mmux_recalc_rate()
685 		div = &mmux->div[1];  in mmux_recalc_rate()
687 	val = div_helper_get_clockdiv(&mmux->common, div);  in mmux_recalc_rate()
698 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_set_rate()  local
702 	if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))  in mmux_set_rate()
705 	if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))  in mmux_set_rate()
706 		div = &mmux->div[0];  in mmux_set_rate()
708 		div = &mmux->div[1];  in mmux_set_rate()
713 	return div_helper_set_rate(&mmux->common, div, val);  in mmux_set_rate()
718 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_get_parent()  local
723 	if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))  in mmux_get_parent()
726 	if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))  in mmux_get_parent()
730 	mux = &mmux->mux[clk_sel];  in mmux_get_parent()
732 	reg = readl(mmux->common.base + mux->reg);  in mmux_get_parent()
734 	return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)];  in mmux_get_parent()
739 	struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);  in mmux_set_parent()  local
743 	s8 clk_sel = mmux->parent2sel[index];  in mmux_set_parent()
746 		cv1800_clk_setbit(&mmux->common, &mmux->bypass);  in mmux_set_parent()
750 	cv1800_clk_clearbit(&mmux->common, &mmux->bypass);  in mmux_set_parent()
753 		cv1800_clk_clearbit(&mmux->common, &mmux->clk_sel);  in mmux_set_parent()
755 		cv1800_clk_setbit(&mmux->common, &mmux->clk_sel);  in mmux_set_parent()
757 	spin_lock_irqsave(mmux->common.lock, flags);  in mmux_set_parent()
759 	mux = &mmux->mux[clk_sel];  in mmux_set_parent()
760 	reg = readl(mmux->common.base + mux->reg);  in mmux_set_parent()
763 	writel(reg, mmux->common.base + mux->reg);  in mmux_set_parent()
765 	spin_unlock_irqrestore(mmux->common.lock, flags);  in mmux_set_parent()