Lines Matching refs:cv1800_clk_setbit

25 	return cv1800_clk_setbit(&gate->common, &gate->gate);  in gate_enable()
90 	return cv1800_clk_setbit(&div->common, &div->gate);  in div_enable()
370 	return cv1800_clk_setbit(&div->div.common, &div->bypass);  in bypass_div_set_parent()
398 	return cv1800_clk_setbit(&mux->common, &mux->gate);  in mux_enable()
579 		return cv1800_clk_setbit(&mux->mux.common, &mux->bypass);  in bypass_mux_set_parent()
623 	return cv1800_clk_setbit(&mmux->common, &mmux->gate);  in mmux_enable()
746 		cv1800_clk_setbit(&mmux->common, &mmux->bypass);  in mmux_set_parent()
755 		cv1800_clk_setbit(&mmux->common, &mmux->clk_sel);  in mmux_set_parent()
797 	cv1800_clk_setbit(&aclk->common, &aclk->src_en);  in aclk_enable()
798 	return cv1800_clk_setbit(&aclk->common, &aclk->output_en);  in aclk_enable()
871 	cv1800_clk_setbit(&aclk->common, &aclk->div_en);  in aclk_set_rate()
872 	cv1800_clk_setbit(&aclk->common, &aclk->div_up);  in aclk_set_rate()