Lines Matching full:hw
71 { .hw = &clk_mipimpll.common.hw },
75 { .hw = &clk_mipimpll.common.hw },
79 { .hw = &clk_fpll.common.hw },
167 { .hw = &clk_cam0pll.common.hw },
187 { .hw = &clk_tpll.common.hw },
188 { .hw = &clk_a0pll.common.hw },
189 { .hw = &clk_mipimpll.common.hw },
190 { .hw = &clk_fpll.common.hw },
211 { .hw = &clk_axi6.div.common.hw },
215 { .hw = &clk_axi6.div.common.hw },
221 { .hw = &clk_fpll.common.hw },
222 { .hw = &clk_disppll.common.hw },
233 { .hw = &clk_axi4.mux.common.hw },
242 { .hw = &clk_xtal_misc.common.hw },
249 { .hw = &clk_disppll.common.hw },
291 { .hw = &clk_1m.common.hw },
294 { .hw = &clk_cam0_200.mux.common.hw },
456 { .hw = &clk_a0pll.common.hw },
457 { .hw = &clk_a24m.common.hw },
629 { .hw = &clk_mipimpll.common.hw },
630 { .hw = &clk_cam0pll.common.hw },
631 { .hw = &clk_disppll.common.hw },
632 { .hw = &clk_fpll.common.hw },
636 { .hw = &clk_disppll.common.hw },
652 { .hw = &clk_axi_vip.mux.common.hw },
789 { .hw = &clk_cam0pll.common.hw },
790 { .hw = &clk_cam0pll_d2.common.hw },
791 { .hw = &clk_cam0pll_d3.common.hw },
792 { .hw = &clk_mipimpll_d3.common.hw },
809 { .hw = &clk_a0pll.common.hw },
810 { .hw = &clk_mipimpll.common.hw },
811 { .hw = &clk_cam1pll.common.hw },
812 { .hw = &clk_fpll.common.hw },
816 { .hw = &clk_disppll.common.hw },
817 { .hw = &clk_mipimpll.common.hw },
818 { .hw = &clk_cam1pll.common.hw },
819 { .hw = &clk_fpll.common.hw },
823 { .hw = &clk_cam1pll.common.hw },
834 { .hw = &clk_axi_video_codec.mux.common.hw },
887 { .hw = &clk_pwm_src.mux.common.hw },
897 { .hw = &clk_tpll.common.hw },
898 { .hw = &clk_a0pll.common.hw },
899 { .hw = &clk_mipimpll.common.hw },
900 { .hw = &clk_mpll.common.hw },
901 { .hw = &clk_fpll.common.hw },
905 { .hw = &clk_tpll.common.hw },
906 { .hw = &clk_a0pll.common.hw },
907 { .hw = &clk_disppll.common.hw },
908 { .hw = &clk_mpll.common.hw },
909 { .hw = &clk_fpll.common.hw },
976 { .hw = &clk_tpll.common.hw },
977 { .hw = &clk_a0pll.common.hw },
978 { .hw = &clk_mipimpll.common.hw },
979 { .hw = &clk_mpll.common.hw },
980 { .hw = &clk_fpll.common.hw },
1027 [CLK_MPLL] = &clk_mpll.common.hw,
1028 [CLK_TPLL] = &clk_tpll.common.hw,
1029 [CLK_FPLL] = &clk_fpll.common.hw,
1030 [CLK_MIPIMPLL] = &clk_mipimpll.common.hw,
1031 [CLK_A0PLL] = &clk_a0pll.common.hw,
1032 [CLK_DISPPLL] = &clk_disppll.common.hw,
1033 [CLK_CAM0PLL] = &clk_cam0pll.common.hw,
1034 [CLK_CAM1PLL] = &clk_cam1pll.common.hw,
1036 [CLK_MIPIMPLL_D3] = &clk_mipimpll_d3.common.hw,
1037 [CLK_CAM0PLL_D2] = &clk_cam0pll_d2.common.hw,
1038 [CLK_CAM0PLL_D3] = &clk_cam0pll_d3.common.hw,
1040 [CLK_TPU] = &clk_tpu.mux.common.hw,
1041 [CLK_TPU_FAB] = &clk_tpu_fab.common.hw,
1042 [CLK_AHB_ROM] = &clk_ahb_rom.common.hw,
1043 [CLK_DDR_AXI_REG] = &clk_ddr_axi_reg.common.hw,
1044 [CLK_RTC_25M] = &clk_rtc_25m.common.hw,
1045 [CLK_SRC_RTC_SYS_0] = &clk_src_rtc_sys_0.div.common.hw,
1046 [CLK_TEMPSEN] = &clk_tempsen.common.hw,
1047 [CLK_SARADC] = &clk_saradc.common.hw,
1048 [CLK_EFUSE] = &clk_efuse.common.hw,
1049 [CLK_APB_EFUSE] = &clk_apb_efuse.common.hw,
1050 [CLK_DEBUG] = &clk_debug.common.hw,
1051 [CLK_AP_DEBUG] = &clk_ap_debug.div.common.hw,
1052 [CLK_XTAL_MISC] = &clk_xtal_misc.common.hw,
1053 [CLK_AXI4_EMMC] = &clk_axi4_emmc.common.hw,
1054 [CLK_EMMC] = &clk_emmc.mux.common.hw,
1055 [CLK_EMMC_100K] = &clk_emmc_100k.common.hw,
1056 [CLK_AXI4_SD0] = &clk_axi4_sd0.common.hw,
1057 [CLK_SD0] = &clk_sd0.mux.common.hw,
1058 [CLK_SD0_100K] = &clk_sd0_100k.common.hw,
1059 [CLK_AXI4_SD1] = &clk_axi4_sd1.common.hw,
1060 [CLK_SD1] = &clk_sd1.mux.common.hw,
1061 [CLK_SD1_100K] = &clk_sd1_100k.common.hw,
1062 [CLK_SPI_NAND] = &clk_spi_nand.mux.common.hw,
1063 [CLK_ETH0_500M] = &clk_eth0_500m.div.common.hw,
1064 [CLK_AXI4_ETH0] = &clk_axi4_eth0.common.hw,
1065 [CLK_ETH1_500M] = &clk_eth1_500m.div.common.hw,
1066 [CLK_AXI4_ETH1] = &clk_axi4_eth1.common.hw,
1067 [CLK_APB_GPIO] = &clk_apb_gpio.common.hw,
1068 [CLK_APB_GPIO_INTR] = &clk_apb_gpio_intr.common.hw,
1069 [CLK_GPIO_DB] = &clk_gpio_db.common.hw,
1070 [CLK_AHB_SF] = &clk_ahb_sf.common.hw,
1071 [CLK_AHB_SF1] = &clk_ahb_sf1.common.hw,
1072 [CLK_A24M] = &clk_a24m.common.hw,
1073 [CLK_AUDSRC] = &clk_audsrc.mux.common.hw,
1074 [CLK_APB_AUDSRC] = &clk_apb_audsrc.common.hw,
1075 [CLK_SDMA_AXI] = &clk_sdma_axi.common.hw,
1076 [CLK_SDMA_AUD0] = &clk_sdma_aud0.mux.common.hw,
1077 [CLK_SDMA_AUD1] = &clk_sdma_aud1.mux.common.hw,
1078 [CLK_SDMA_AUD2] = &clk_sdma_aud2.mux.common.hw,
1079 [CLK_SDMA_AUD3] = &clk_sdma_aud3.mux.common.hw,
1080 [CLK_I2C] = &clk_i2c.div.common.hw,
1081 [CLK_APB_I2C] = &clk_apb_i2c.common.hw,
1082 [CLK_APB_I2C0] = &clk_apb_i2c0.common.hw,
1083 [CLK_APB_I2C1] = &clk_apb_i2c1.common.hw,
1084 [CLK_APB_I2C2] = &clk_apb_i2c2.common.hw,
1085 [CLK_APB_I2C3] = &clk_apb_i2c3.common.hw,
1086 [CLK_APB_I2C4] = &clk_apb_i2c4.common.hw,
1087 [CLK_APB_WDT] = &clk_apb_wdt.common.hw,
1088 [CLK_PWM_SRC] = &clk_pwm_src.mux.common.hw,
1089 [CLK_PWM] = &clk_pwm.common.hw,
1090 [CLK_SPI] = &clk_spi.div.common.hw,
1091 [CLK_APB_SPI0] = &clk_apb_spi0.common.hw,
1092 [CLK_APB_SPI1] = &clk_apb_spi1.common.hw,
1093 [CLK_APB_SPI2] = &clk_apb_spi2.common.hw,
1094 [CLK_APB_SPI3] = &clk_apb_spi3.common.hw,
1095 [CLK_1M] = &clk_1m.common.hw,
1096 [CLK_CAM0_200] = &clk_cam0_200.mux.common.hw,
1097 [CLK_PM] = &clk_pm.common.hw,
1098 [CLK_TIMER0] = &clk_timer0.common.hw,
1099 [CLK_TIMER1] = &clk_timer1.common.hw,
1100 [CLK_TIMER2] = &clk_timer2.common.hw,
1101 [CLK_TIMER3] = &clk_timer3.common.hw,
1102 [CLK_TIMER4] = &clk_timer4.common.hw,
1103 [CLK_TIMER5] = &clk_timer5.common.hw,
1104 [CLK_TIMER6] = &clk_timer6.common.hw,
1105 [CLK_TIMER7] = &clk_timer7.common.hw,
1106 [CLK_UART0] = &clk_uart0.common.hw,
1107 [CLK_APB_UART0] = &clk_apb_uart0.common.hw,
1108 [CLK_UART1] = &clk_uart1.common.hw,
1109 [CLK_APB_UART1] = &clk_apb_uart1.common.hw,
1110 [CLK_UART2] = &clk_uart2.common.hw,
1111 [CLK_APB_UART2] = &clk_apb_uart2.common.hw,
1112 [CLK_UART3] = &clk_uart3.common.hw,
1113 [CLK_APB_UART3] = &clk_apb_uart3.common.hw,
1114 [CLK_UART4] = &clk_uart4.common.hw,
1115 [CLK_APB_UART4] = &clk_apb_uart4.common.hw,
1116 [CLK_APB_I2S0] = &clk_apb_i2s0.common.hw,
1117 [CLK_APB_I2S1] = &clk_apb_i2s1.common.hw,
1118 [CLK_APB_I2S2] = &clk_apb_i2s2.common.hw,
1119 [CLK_APB_I2S3] = &clk_apb_i2s3.common.hw,
1120 [CLK_AXI4_USB] = &clk_axi4_usb.common.hw,
1121 [CLK_APB_USB] = &clk_apb_usb.common.hw,
1122 [CLK_USB_125M] = &clk_usb_125m.div.common.hw,
1123 [CLK_USB_33K] = &clk_usb_33k.common.hw,
1124 [CLK_USB_12M] = &clk_usb_12m.div.common.hw,
1125 [CLK_AXI4] = &clk_axi4.mux.common.hw,
1126 [CLK_AXI6] = &clk_axi6.div.common.hw,
1127 [CLK_DSI_ESC] = &clk_dsi_esc.div.common.hw,
1128 [CLK_AXI_VIP] = &clk_axi_vip.mux.common.hw,
1129 [CLK_SRC_VIP_SYS_0] = &clk_src_vip_sys_0.mux.common.hw,
1130 [CLK_SRC_VIP_SYS_1] = &clk_src_vip_sys_1.mux.common.hw,
1131 [CLK_SRC_VIP_SYS_2] = &clk_src_vip_sys_2.mux.common.hw,
1132 [CLK_SRC_VIP_SYS_3] = &clk_src_vip_sys_3.mux.common.hw,
1133 [CLK_SRC_VIP_SYS_4] = &clk_src_vip_sys_4.mux.common.hw,
1134 [CLK_CSI_BE_VIP] = &clk_csi_be_vip.common.hw,
1135 [CLK_CSI_MAC0_VIP] = &clk_csi_mac0_vip.common.hw,
1136 [CLK_CSI_MAC1_VIP] = &clk_csi_mac1_vip.common.hw,
1137 [CLK_CSI_MAC2_VIP] = &clk_csi_mac2_vip.common.hw,
1138 [CLK_CSI0_RX_VIP] = &clk_csi0_rx_vip.common.hw,
1139 [CLK_CSI1_RX_VIP] = &clk_csi1_rx_vip.common.hw,
1140 [CLK_ISP_TOP_VIP] = &clk_isp_top_vip.common.hw,
1141 [CLK_IMG_D_VIP] = &clk_img_d_vip.common.hw,
1142 [CLK_IMG_V_VIP] = &clk_img_v_vip.common.hw,
1143 [CLK_SC_TOP_VIP] = &clk_sc_top_vip.common.hw,
1144 [CLK_SC_D_VIP] = &clk_sc_d_vip.common.hw,
1145 [CLK_SC_V1_VIP] = &clk_sc_v1_vip.common.hw,
1146 [CLK_SC_V2_VIP] = &clk_sc_v2_vip.common.hw,
1147 [CLK_SC_V3_VIP] = &clk_sc_v3_vip.common.hw,
1148 [CLK_DWA_VIP] = &clk_dwa_vip.common.hw,
1149 [CLK_BT_VIP] = &clk_bt_vip.common.hw,
1150 [CLK_DISP_VIP] = &clk_disp_vip.common.hw,
1151 [CLK_DSI_MAC_VIP] = &clk_dsi_mac_vip.common.hw,
1152 [CLK_LVDS0_VIP] = &clk_lvds0_vip.common.hw,
1153 [CLK_LVDS1_VIP] = &clk_lvds1_vip.common.hw,
1154 [CLK_PAD_VI_VIP] = &clk_pad_vi_vip.common.hw,
1155 [CLK_PAD_VI1_VIP] = &clk_pad_vi1_vip.common.hw,
1156 [CLK_PAD_VI2_VIP] = &clk_pad_vi2_vip.common.hw,
1157 [CLK_CFG_REG_VIP] = &clk_cfg_reg_vip.common.hw,
1158 [CLK_VIP_IP0] = &clk_vip_ip0.common.hw,
1159 [CLK_VIP_IP1] = &clk_vip_ip1.common.hw,
1160 [CLK_VIP_IP2] = &clk_vip_ip2.common.hw,
1161 [CLK_VIP_IP3] = &clk_vip_ip3.common.hw,
1162 [CLK_IVE_VIP] = &clk_ive_vip.common.hw,
1163 [CLK_RAW_VIP] = &clk_raw_vip.common.hw,
1164 [CLK_OSDC_VIP] = &clk_osdc_vip.common.hw,
1165 [CLK_CAM0_VIP] = &clk_cam0_vip.common.hw,
1166 [CLK_AXI_VIDEO_CODEC] = &clk_axi_video_codec.mux.common.hw,
1167 [CLK_VC_SRC0] = &clk_vc_src0.mux.common.hw,
1168 [CLK_VC_SRC1] = &clk_vc_src1.div.common.hw,
1169 [CLK_VC_SRC2] = &clk_vc_src2.div.common.hw,
1170 [CLK_H264C] = &clk_h264c.common.hw,
1171 [CLK_APB_H264C] = &clk_apb_h264c.common.hw,
1172 [CLK_H265C] = &clk_h265c.common.hw,
1173 [CLK_APB_H265C] = &clk_apb_h265c.common.hw,
1174 [CLK_JPEG] = &clk_jpeg.common.hw,
1175 [CLK_APB_JPEG] = &clk_apb_jpeg.common.hw,
1176 [CLK_CAM0] = &clk_cam0.common.hw,
1177 [CLK_CAM1] = &clk_cam1.common.hw,
1178 [CLK_WGN] = &clk_wgn.common.hw,
1179 [CLK_WGN0] = &clk_wgn0.common.hw,
1180 [CLK_WGN1] = &clk_wgn1.common.hw,
1181 [CLK_WGN2] = &clk_wgn2.common.hw,
1182 [CLK_KEYSCAN] = &clk_keyscan.common.hw,
1183 [CLK_CFG_REG_VC] = &clk_cfg_reg_vc.common.hw,
1184 [CLK_C906_0] = &clk_c906_0.common.hw,
1185 [CLK_C906_1] = &clk_c906_1.common.hw,
1186 [CLK_A53] = &clk_a53.common.hw,
1187 [CLK_CPU_AXI0] = &clk_cpu_axi0.div.common.hw,
1188 [CLK_CPU_GIC] = &clk_cpu_gic.div.common.hw,
1189 [CLK_XTAL_AP] = &clk_xtal_ap.common.hw,
1258 [CLK_MPLL] = &clk_mpll.common.hw,
1259 [CLK_TPLL] = &clk_tpll.common.hw,
1260 [CLK_FPLL] = &clk_fpll.common.hw,
1261 [CLK_MIPIMPLL] = &clk_mipimpll.common.hw,
1262 [CLK_A0PLL] = &clk_a0pll.common.hw,
1263 [CLK_DISPPLL] = &clk_disppll.common.hw,
1264 [CLK_CAM0PLL] = &clk_cam0pll.common.hw,
1265 [CLK_CAM1PLL] = &clk_cam1pll.common.hw,
1267 [CLK_MIPIMPLL_D3] = &clk_mipimpll_d3.common.hw,
1268 [CLK_CAM0PLL_D2] = &clk_cam0pll_d2.common.hw,
1269 [CLK_CAM0PLL_D3] = &clk_cam0pll_d3.common.hw,
1271 [CLK_TPU] = &clk_tpu.mux.common.hw,
1272 [CLK_TPU_FAB] = &clk_tpu_fab.common.hw,
1273 [CLK_AHB_ROM] = &clk_ahb_rom.common.hw,
1274 [CLK_DDR_AXI_REG] = &clk_ddr_axi_reg.common.hw,
1275 [CLK_RTC_25M] = &clk_rtc_25m.common.hw,
1276 [CLK_SRC_RTC_SYS_0] = &clk_src_rtc_sys_0.div.common.hw,
1277 [CLK_TEMPSEN] = &clk_tempsen.common.hw,
1278 [CLK_SARADC] = &clk_saradc.common.hw,
1279 [CLK_EFUSE] = &clk_efuse.common.hw,
1280 [CLK_APB_EFUSE] = &clk_apb_efuse.common.hw,
1281 [CLK_DEBUG] = &clk_debug.common.hw,
1282 [CLK_AP_DEBUG] = &clk_ap_debug.div.common.hw,
1283 [CLK_XTAL_MISC] = &clk_xtal_misc.common.hw,
1284 [CLK_AXI4_EMMC] = &clk_axi4_emmc.common.hw,
1285 [CLK_EMMC] = &clk_emmc.mux.common.hw,
1286 [CLK_EMMC_100K] = &clk_emmc_100k.common.hw,
1287 [CLK_AXI4_SD0] = &clk_axi4_sd0.common.hw,
1288 [CLK_SD0] = &clk_sd0.mux.common.hw,
1289 [CLK_SD0_100K] = &clk_sd0_100k.common.hw,
1290 [CLK_AXI4_SD1] = &clk_axi4_sd1.common.hw,
1291 [CLK_SD1] = &clk_sd1.mux.common.hw,
1292 [CLK_SD1_100K] = &clk_sd1_100k.common.hw,
1293 [CLK_SPI_NAND] = &clk_spi_nand.mux.common.hw,
1294 [CLK_ETH0_500M] = &clk_eth0_500m.div.common.hw,
1295 [CLK_AXI4_ETH0] = &clk_axi4_eth0.common.hw,
1296 [CLK_ETH1_500M] = &clk_eth1_500m.div.common.hw,
1297 [CLK_AXI4_ETH1] = &clk_axi4_eth1.common.hw,
1298 [CLK_APB_GPIO] = &clk_apb_gpio.common.hw,
1299 [CLK_APB_GPIO_INTR] = &clk_apb_gpio_intr.common.hw,
1300 [CLK_GPIO_DB] = &clk_gpio_db.common.hw,
1301 [CLK_AHB_SF] = &clk_ahb_sf.common.hw,
1302 [CLK_AHB_SF1] = &clk_ahb_sf1.common.hw,
1303 [CLK_A24M] = &clk_a24m.common.hw,
1304 [CLK_AUDSRC] = &clk_audsrc.mux.common.hw,
1305 [CLK_APB_AUDSRC] = &clk_apb_audsrc.common.hw,
1306 [CLK_SDMA_AXI] = &clk_sdma_axi.common.hw,
1307 [CLK_SDMA_AUD0] = &clk_sdma_aud0.mux.common.hw,
1308 [CLK_SDMA_AUD1] = &clk_sdma_aud1.mux.common.hw,
1309 [CLK_SDMA_AUD2] = &clk_sdma_aud2.mux.common.hw,
1310 [CLK_SDMA_AUD3] = &clk_sdma_aud3.mux.common.hw,
1311 [CLK_I2C] = &clk_i2c.div.common.hw,
1312 [CLK_APB_I2C] = &clk_apb_i2c.common.hw,
1313 [CLK_APB_I2C0] = &clk_apb_i2c0.common.hw,
1314 [CLK_APB_I2C1] = &clk_apb_i2c1.common.hw,
1315 [CLK_APB_I2C2] = &clk_apb_i2c2.common.hw,
1316 [CLK_APB_I2C3] = &clk_apb_i2c3.common.hw,
1317 [CLK_APB_I2C4] = &clk_apb_i2c4.common.hw,
1318 [CLK_APB_WDT] = &clk_apb_wdt.common.hw,
1319 [CLK_PWM_SRC] = &clk_pwm_src.mux.common.hw,
1320 [CLK_PWM] = &clk_pwm.common.hw,
1321 [CLK_SPI] = &clk_spi.div.common.hw,
1322 [CLK_APB_SPI0] = &clk_apb_spi0.common.hw,
1323 [CLK_APB_SPI1] = &clk_apb_spi1.common.hw,
1324 [CLK_APB_SPI2] = &clk_apb_spi2.common.hw,
1325 [CLK_APB_SPI3] = &clk_apb_spi3.common.hw,
1326 [CLK_1M] = &clk_1m.common.hw,
1327 [CLK_CAM0_200] = &clk_cam0_200.mux.common.hw,
1328 [CLK_PM] = &clk_pm.common.hw,
1329 [CLK_TIMER0] = &clk_timer0.common.hw,
1330 [CLK_TIMER1] = &clk_timer1.common.hw,
1331 [CLK_TIMER2] = &clk_timer2.common.hw,
1332 [CLK_TIMER3] = &clk_timer3.common.hw,
1333 [CLK_TIMER4] = &clk_timer4.common.hw,
1334 [CLK_TIMER5] = &clk_timer5.common.hw,
1335 [CLK_TIMER6] = &clk_timer6.common.hw,
1336 [CLK_TIMER7] = &clk_timer7.common.hw,
1337 [CLK_UART0] = &clk_uart0.common.hw,
1338 [CLK_APB_UART0] = &clk_apb_uart0.common.hw,
1339 [CLK_UART1] = &clk_uart1.common.hw,
1340 [CLK_APB_UART1] = &clk_apb_uart1.common.hw,
1341 [CLK_UART2] = &clk_uart2.common.hw,
1342 [CLK_APB_UART2] = &clk_apb_uart2.common.hw,
1343 [CLK_UART3] = &clk_uart3.common.hw,
1344 [CLK_APB_UART3] = &clk_apb_uart3.common.hw,
1345 [CLK_UART4] = &clk_uart4.common.hw,
1346 [CLK_APB_UART4] = &clk_apb_uart4.common.hw,
1347 [CLK_APB_I2S0] = &clk_apb_i2s0.common.hw,
1348 [CLK_APB_I2S1] = &clk_apb_i2s1.common.hw,
1349 [CLK_APB_I2S2] = &clk_apb_i2s2.common.hw,
1350 [CLK_APB_I2S3] = &clk_apb_i2s3.common.hw,
1351 [CLK_AXI4_USB] = &clk_axi4_usb.common.hw,
1352 [CLK_APB_USB] = &clk_apb_usb.common.hw,
1353 [CLK_USB_125M] = &clk_usb_125m.div.common.hw,
1354 [CLK_USB_33K] = &clk_usb_33k.common.hw,
1355 [CLK_USB_12M] = &clk_usb_12m.div.common.hw,
1356 [CLK_AXI4] = &clk_axi4.mux.common.hw,
1357 [CLK_AXI6] = &clk_axi6.div.common.hw,
1358 [CLK_DSI_ESC] = &clk_dsi_esc.div.common.hw,
1359 [CLK_AXI_VIP] = &clk_axi_vip.mux.common.hw,
1360 [CLK_SRC_VIP_SYS_0] = &clk_src_vip_sys_0.mux.common.hw,
1361 [CLK_SRC_VIP_SYS_1] = &clk_src_vip_sys_1.mux.common.hw,
1362 [CLK_SRC_VIP_SYS_2] = &clk_src_vip_sys_2.mux.common.hw,
1363 [CLK_SRC_VIP_SYS_3] = &clk_src_vip_sys_3.mux.common.hw,
1364 [CLK_SRC_VIP_SYS_4] = &clk_src_vip_sys_4.mux.common.hw,
1365 [CLK_CSI_BE_VIP] = &clk_csi_be_vip.common.hw,
1366 [CLK_CSI_MAC0_VIP] = &clk_csi_mac0_vip.common.hw,
1367 [CLK_CSI_MAC1_VIP] = &clk_csi_mac1_vip.common.hw,
1368 [CLK_CSI_MAC2_VIP] = &clk_csi_mac2_vip.common.hw,
1369 [CLK_CSI0_RX_VIP] = &clk_csi0_rx_vip.common.hw,
1370 [CLK_CSI1_RX_VIP] = &clk_csi1_rx_vip.common.hw,
1371 [CLK_ISP_TOP_VIP] = &clk_isp_top_vip.common.hw,
1372 [CLK_IMG_D_VIP] = &clk_img_d_vip.common.hw,
1373 [CLK_IMG_V_VIP] = &clk_img_v_vip.common.hw,
1374 [CLK_SC_TOP_VIP] = &clk_sc_top_vip.common.hw,
1375 [CLK_SC_D_VIP] = &clk_sc_d_vip.common.hw,
1376 [CLK_SC_V1_VIP] = &clk_sc_v1_vip.common.hw,
1377 [CLK_SC_V2_VIP] = &clk_sc_v2_vip.common.hw,
1378 [CLK_SC_V3_VIP] = &clk_sc_v3_vip.common.hw,
1379 [CLK_DWA_VIP] = &clk_dwa_vip.common.hw,
1380 [CLK_BT_VIP] = &clk_bt_vip.common.hw,
1381 [CLK_DISP_VIP] = &clk_disp_vip.common.hw,
1382 [CLK_DSI_MAC_VIP] = &clk_dsi_mac_vip.common.hw,
1383 [CLK_LVDS0_VIP] = &clk_lvds0_vip.common.hw,
1384 [CLK_LVDS1_VIP] = &clk_lvds1_vip.common.hw,
1385 [CLK_PAD_VI_VIP] = &clk_pad_vi_vip.common.hw,
1386 [CLK_PAD_VI1_VIP] = &clk_pad_vi1_vip.common.hw,
1387 [CLK_PAD_VI2_VIP] = &clk_pad_vi2_vip.common.hw,
1388 [CLK_CFG_REG_VIP] = &clk_cfg_reg_vip.common.hw,
1389 [CLK_VIP_IP0] = &clk_vip_ip0.common.hw,
1390 [CLK_VIP_IP1] = &clk_vip_ip1.common.hw,
1391 [CLK_VIP_IP2] = &clk_vip_ip2.common.hw,
1392 [CLK_VIP_IP3] = &clk_vip_ip3.common.hw,
1393 [CLK_IVE_VIP] = &clk_ive_vip.common.hw,
1394 [CLK_RAW_VIP] = &clk_raw_vip.common.hw,
1395 [CLK_OSDC_VIP] = &clk_osdc_vip.common.hw,
1396 [CLK_CAM0_VIP] = &clk_cam0_vip.common.hw,
1397 [CLK_AXI_VIDEO_CODEC] = &clk_axi_video_codec.mux.common.hw,
1398 [CLK_VC_SRC0] = &clk_vc_src0.mux.common.hw,
1399 [CLK_VC_SRC1] = &clk_vc_src1.div.common.hw,
1400 [CLK_VC_SRC2] = &clk_vc_src2.div.common.hw,
1401 [CLK_H264C] = &clk_h264c.common.hw,
1402 [CLK_APB_H264C] = &clk_apb_h264c.common.hw,
1403 [CLK_H265C] = &clk_h265c.common.hw,
1404 [CLK_APB_H265C] = &clk_apb_h265c.common.hw,
1405 [CLK_JPEG] = &clk_jpeg.common.hw,
1406 [CLK_APB_JPEG] = &clk_apb_jpeg.common.hw,
1407 [CLK_CAM0] = &clk_cam0.common.hw,
1408 [CLK_CAM1] = &clk_cam1.common.hw,
1409 [CLK_WGN] = &clk_wgn.common.hw,
1410 [CLK_WGN0] = &clk_wgn0.common.hw,
1411 [CLK_WGN1] = &clk_wgn1.common.hw,
1412 [CLK_WGN2] = &clk_wgn2.common.hw,
1413 [CLK_KEYSCAN] = &clk_keyscan.common.hw,
1414 [CLK_CFG_REG_VC] = &clk_cfg_reg_vc.common.hw,
1415 [CLK_C906_0] = &clk_c906_0.common.hw,
1416 [CLK_C906_1] = &clk_c906_1.common.hw,
1417 [CLK_A53] = &clk_a53.common.hw,
1418 [CLK_CPU_AXI0] = &clk_cpu_axi0.div.common.hw,
1419 [CLK_CPU_GIC] = &clk_cpu_gic.div.common.hw,
1420 [CLK_XTAL_AP] = &clk_xtal_ap.common.hw,
1421 [CLK_DISP_SRC_VIP] = &clk_disp_src_vip.div.common.hw,
1464 struct clk_hw *hw = desc->clks_data->hws[i]; in cv1800_clk_init_ctrl() local
1468 if (!hw) in cv1800_clk_init_ctrl()
1471 name = hw->init->name; in cv1800_clk_init_ctrl()
1473 common = hw_to_cv1800_clk_common(hw); in cv1800_clk_init_ctrl()
1477 ret = devm_clk_hw_register(dev, hw); in cv1800_clk_init_ctrl()