1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
44 	unsigned long fdiv, reg, rdiv, qdiv;  in n5x_clk_pll_recalc_rate()  local
47 	/* read VCO1 reg for numerator and denominator */  in n5x_clk_pll_recalc_rate()
48 	reg = readl(socfpgaclk->hw.reg + 0x8);  in n5x_clk_pll_recalc_rate()
49 	fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT;  in n5x_clk_pll_recalc_rate()
50 	rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK);  in n5x_clk_pll_recalc_rate()
51 	qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT;  in n5x_clk_pll_recalc_rate()
55 		qdiv--;  in n5x_clk_pll_recalc_rate()
65 	unsigned long arefdiv, reg, mdiv;  in agilex_clk_pll_recalc_rate()  local
68 	/* read VCO1 reg for numerator and denominator */  in agilex_clk_pll_recalc_rate()
69 	reg = readl(socfpgaclk->hw.reg);  in agilex_clk_pll_recalc_rate()
70 	arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;  in agilex_clk_pll_recalc_rate()
75 	reg = readl(socfpgaclk->hw.reg + 0x24);  in agilex_clk_pll_recalc_rate()
76 	mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;  in agilex_clk_pll_recalc_rate()
88 	unsigned long reg;  in clk_pll_recalc_rate()  local
91 	/* read VCO1 reg for numerator and denominator */  in clk_pll_recalc_rate()
92 	reg = readl(socfpgaclk->hw.reg);  in clk_pll_recalc_rate()
93 	refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;  in clk_pll_recalc_rate()
99 	reg = readl(socfpgaclk->hw.reg + 0x4);  in clk_pll_recalc_rate()
100 	mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;  in clk_pll_recalc_rate()
112 	div = ((readl(socfpgaclk->hw.reg) &  in clk_boot_clk_recalc_rate()
125 	pll_src = readl(socfpgaclk->hw.reg);  in clk_pll_get_parent()
135 	pll_src = readl(socfpgaclk->hw.reg);  in clk_boot_get_parent()
143 	u32 reg;  in clk_pll_prepare()  local
146 	reg = readl(socfpgaclk->hw.reg);  in clk_pll_prepare()
147 	reg |= SOCFPGA_PLL_RESET_MASK;  in clk_pll_prepare()
148 	writel(reg, socfpgaclk->hw.reg);  in clk_pll_prepare()
156 	u32 reg;  in n5x_clk_pll_prepare()  local
159 	reg = readl(socfpgaclk->hw.reg + 0x4);  in n5x_clk_pll_prepare()
160 	reg |= SOCFPGA_PLL_RESET_MASK;  in n5x_clk_pll_prepare()
161 	writel(reg, socfpgaclk->hw.reg + 0x4);  in n5x_clk_pll_prepare()
191 			     void __iomem *reg)  in s10_register_pll()  argument
195 	struct clk_init_data init;  in s10_register_pll()  local
196 	const char *name = clks->name;  in s10_register_pll()
203 	pll_clk->hw.reg = reg + clks->offset;  in s10_register_pll()
206 		init.ops = &clk_boot_ops;  in s10_register_pll()
208 		init.ops = &clk_pll_ops;  in s10_register_pll()
210 	init.name = name;  in s10_register_pll()
211 	init.flags = clks->flags;  in s10_register_pll()
213 	init.num_parents = clks->num_parents;  in s10_register_pll()
214 	init.parent_names = NULL;  in s10_register_pll()
215 	init.parent_data = clks->parent_data;  in s10_register_pll()
216 	pll_clk->hw.hw.init = &init;  in s10_register_pll()
218 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;  in s10_register_pll()
220 	hw_clk = &pll_clk->hw.hw;  in s10_register_pll()
231 				void __iomem *reg)  in agilex_register_pll()  argument
235 	struct clk_init_data init;  in agilex_register_pll()  local
236 	const char *name = clks->name;  in agilex_register_pll()
243 	pll_clk->hw.reg = reg + clks->offset;  in agilex_register_pll()
246 		init.ops = &clk_boot_ops;  in agilex_register_pll()
248 		init.ops = &agilex_clk_pll_ops;  in agilex_register_pll()
250 	init.name = name;  in agilex_register_pll()
251 	init.flags = clks->flags;  in agilex_register_pll()
253 	init.num_parents = clks->num_parents;  in agilex_register_pll()
254 	init.parent_names = NULL;  in agilex_register_pll()
255 	init.parent_data = clks->parent_data;  in agilex_register_pll()
256 	pll_clk->hw.hw.init = &init;  in agilex_register_pll()
258 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;  in agilex_register_pll()
259 	hw_clk = &pll_clk->hw.hw;  in agilex_register_pll()
270 			     void __iomem *reg)  in n5x_register_pll()  argument
274 	struct clk_init_data init;  in n5x_register_pll()  local
275 	const char *name = clks->name;  in n5x_register_pll()
282 	pll_clk->hw.reg = reg + clks->offset;  in n5x_register_pll()
285 		init.ops = &clk_boot_ops;  in n5x_register_pll()
287 		init.ops = &n5x_clk_pll_ops;  in n5x_register_pll()
289 	init.name = name;  in n5x_register_pll()
290 	init.flags = clks->flags;  in n5x_register_pll()
292 	init.num_parents = clks->num_parents;  in n5x_register_pll()
293 	init.parent_names = NULL;  in n5x_register_pll()
294 	init.parent_data = clks->parent_data;  in n5x_register_pll()
295 	pll_clk->hw.hw.init = &init;  in n5x_register_pll()
297 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;  in n5x_register_pll()
298 	hw_clk = &pll_clk->hw.hw;  in n5x_register_pll()