1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
38 	unsigned long divf, divq, reg;  in clk_pll_recalc_rate()  local
41 	/* read VCO1 reg for numerator and denominator */  in clk_pll_recalc_rate()
42 	reg = readl(socfpgaclk->hw.reg + 0x4);  in clk_pll_recalc_rate()
43 	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;  in clk_pll_recalc_rate()
44 	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;  in clk_pll_recalc_rate()
55 	pll_src = readl(socfpgaclk->hw.reg);  in clk_pll_get_parent()
69 	u32 reg;  in __socfpga_pll_init()  local
72 	const char *clk_name = node->name;  in __socfpga_pll_init()
74 	struct clk_init_data init;  in __socfpga_pll_init()  local
79 	of_property_read_u32(node, "reg", &reg);  in __socfpga_pll_init()
85 	clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");  in __socfpga_pll_init()
89 	pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;  in __socfpga_pll_init()
91 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_pll_init()
93 	init.name = clk_name;  in __socfpga_pll_init()
94 	init.ops = ops;  in __socfpga_pll_init()
95 	init.flags = 0;  in __socfpga_pll_init()
100 	init.num_parents = i;  in __socfpga_pll_init()
101 	init.parent_names = parent_name;  in __socfpga_pll_init()
102 	pll_clk->hw.hw.init = &init;  in __socfpga_pll_init()
104 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;  in __socfpga_pll_init()
105 	hw_clk = &pll_clk->hw.hw;  in __socfpga_pll_init()