clk/socfpga/clk-pll-a10.c

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include "clk.h"
42 	reg = readl(socfpgaclk->hw.reg + 0x4);  in clk_pll_recalc_rate()
55 	pll_src = readl(socfpgaclk->hw.reg);  in clk_pll_get_parent()
72 	const char *clk_name = node->name;  in __socfpga_pll_init()
85 	clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");  in __socfpga_pll_init()
89 	pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;  in __socfpga_pll_init()
91 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_pll_init()
102 	pll_clk->hw.hw.init = &init;  in __socfpga_pll_init()
104 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;  in __socfpga_pll_init()
105 	hw_clk = &pll_clk->hw.hw;  in __socfpga_pll_init()