Lines Matching +full:0 +full:x1ff
28 #define PRCI_COREPLLCFG0_OFFSET 0x4
29 #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
30 #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
32 #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
34 #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
36 #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
38 #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
40 #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
42 #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
45 #define PRCI_COREPLLCFG1_OFFSET 0x8
47 #define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
50 #define PRCI_DDRPLLCFG0_OFFSET 0xc
51 #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
52 #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
54 #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
56 #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
58 #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
60 #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
62 #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
64 #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
67 #define PRCI_DDRPLLCFG1_OFFSET 0x10
69 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
72 #define PRCI_PCIE_AUX_OFFSET 0x14
73 #define PRCI_PCIE_AUX_EN_SHIFT 0
74 #define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT)
77 #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
78 #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
79 #define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
81 #define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
83 #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
85 #define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
87 #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
89 #define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
91 #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
94 #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
96 #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
99 #define PRCI_CORECLKSEL_OFFSET 0x24
100 #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
102 (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
105 #define PRCI_DEVICESRESETREG_OFFSET 0x28
106 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
108 (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
111 (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
114 (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
117 (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
120 (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
123 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
128 #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
131 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
134 #define PRCI_CLTXPLLCFG0_OFFSET 0x30
135 #define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0
136 #define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT)
138 #define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT)
140 #define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT)
142 #define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT)
144 #define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT)
146 #define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT)
148 #define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT)
151 #define PRCI_CLTXPLLCFG1_OFFSET 0x34
153 #define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT)
156 #define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38
159 #define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c
161 #define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT)
164 #define PRCI_COREPLLSEL_OFFSET 0x40
165 #define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0
167 (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT)
170 #define PRCI_HFPCLKPLLCFG0_OFFSET 0x50
171 #define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0
173 (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT)
176 (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT)
179 (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT)
182 (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT)
185 (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT)
188 (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT)
191 (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT)
194 #define PRCI_HFPCLKPLLCFG1_OFFSET 0x54
197 (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT)
200 #define PRCI_HFPCLKPLLSEL_OFFSET 0x58
201 #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0
203 (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT)
206 #define PRCI_HFPCLKPLLDIV_OFFSET 0x5c
209 #define PRCI_PRCIPLL_OFFSET 0xe0
212 #define PRCI_PROCMONCFG_OFFSET 0xf0