Lines Matching +full:exynos +full:- +full:audss +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on Exynos Audio Subsystem Clock Controller driver:
10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/s5pv210-audss.h>
70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe()
76 clk_data = devm_kzalloc(&pdev->dev, in s5pv210_audss_clk_probe()
81 return -ENOMEM; in s5pv210_audss_clk_probe()
83 clk_data->num = AUDSS_MAX_CLKS; in s5pv210_audss_clk_probe()
84 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
86 hclk = devm_clk_get(&pdev->dev, "hclk"); in s5pv210_audss_clk_probe()
88 dev_err(&pdev->dev, "failed to get hclk clock\n"); in s5pv210_audss_clk_probe()
92 pll_in = devm_clk_get(&pdev->dev, "fout_epll"); in s5pv210_audss_clk_probe()
94 dev_err(&pdev->dev, "failed to get fout_epll clock\n"); in s5pv210_audss_clk_probe()
98 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0"); in s5pv210_audss_clk_probe()
100 dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n"); in s5pv210_audss_clk_probe()
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
106 pll_ref = devm_clk_get(&pdev->dev, "xxti"); in s5pv210_audss_clk_probe()
161 for (i = 0; i < clk_data->num; i++) { in s5pv210_audss_clk_probe()
163 dev_err(&pdev->dev, "failed to register clock %d\n", i); in s5pv210_audss_clk_probe()
169 ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, in s5pv210_audss_clk_probe()
172 dev_err(&pdev->dev, "failed to add clock provider\n"); in s5pv210_audss_clk_probe()
183 for (i = 0; i < clk_data->num; i++) { in s5pv210_audss_clk_probe()
192 { .compatible = "samsung,s5pv210-audss-clock", },
198 .name = "s5pv210-audss-clk",