Lines Matching full:pll
6 * This file contains the utility functions to register the pll clocks.
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
60 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
78 /* Wait until the PLL is locked */
79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, in samsung_pll_lock_wait() argument
99 if (readl_relaxed(pll->con_reg) & reg_mask) in samsung_pll_lock_wait()
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
118 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
121 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
122 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
123 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll3xxx_enable()
130 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable() local
133 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
134 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
135 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
152 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
156 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
185 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
189 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
222 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate() local
226 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
251 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate() local
256 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
258 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll35xx_set_rate()
263 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
269 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
274 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
276 pll->lock_reg); in samsung_pll35xx_set_rate()
278 /* Change PLL PMS values */ in samsung_pll35xx_set_rate()
285 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
287 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll35xx_set_rate()
288 if (tmp & BIT(pll->enable_offs)) in samsung_pll35xx_set_rate()
289 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll35xx_set_rate()
326 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate() local
331 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
332 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
361 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate() local
365 rate = samsung_get_pll_settings(pll, drate); in samsung_pll36xx_set_rate()
367 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll36xx_set_rate()
372 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
373 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
379 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
384 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
385 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
387 /* Change PLL PMS values */ in samsung_pll36xx_set_rate()
394 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
398 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
400 if (pll_con0 & BIT(pll->enable_offs)) in samsung_pll36xx_set_rate()
401 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll36xx_set_rate()
439 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_recalc_rate() local
443 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_recalc_rate()
444 if (pll->type != pll_1418x) in samsung_pll0822x_recalc_rate()
452 if (pll->type == pll_0516x) in samsung_pll0822x_recalc_rate()
464 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_set_rate() local
467 if (pll->type != pll_1418x) in samsung_pll0822x_set_rate()
473 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0822x_set_rate()
475 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0822x_set_rate()
480 /* Change PLL PMS values */ in samsung_pll0822x_set_rate()
481 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_set_rate()
489 /* Set PLL lock time */ in samsung_pll0822x_set_rate()
491 pll->lock_reg); in samsung_pll0822x_set_rate()
494 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0822x_set_rate()
496 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0822x_set_rate()
497 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0822x_set_rate()
498 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0822x_set_rate()
535 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_recalc_rate() local
540 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_recalc_rate()
541 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_recalc_rate()
558 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_set_rate() local
562 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0831x_set_rate()
564 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0831x_set_rate()
569 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_set_rate()
570 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_set_rate()
572 /* Change PLL PMSK values */ in samsung_pll0831x_set_rate()
586 /* Set PLL lock time */ in samsung_pll0831x_set_rate()
587 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); in samsung_pll0831x_set_rate()
590 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0831x_set_rate()
591 writel_relaxed(pll_con5, pll->con_reg + 8); in samsung_pll0831x_set_rate()
593 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0831x_set_rate()
594 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0831x_set_rate()
595 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0831x_set_rate()
633 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate() local
637 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
642 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
667 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate() local
672 rate = samsung_get_pll_settings(pll, drate); in samsung_pll45xx_set_rate()
674 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll45xx_set_rate()
679 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
680 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
686 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
691 /* Set PLL PMS values. */ in samsung_pll45xx_set_rate()
699 /* Set PLL AFC value. */ in samsung_pll45xx_set_rate()
700 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
704 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
705 switch (pll->type) { in samsung_pll45xx_set_rate()
707 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
710 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
717 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
718 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
720 /* Wait for PLL lock */ in samsung_pll45xx_set_rate()
721 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); in samsung_pll45xx_set_rate()
766 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate() local
770 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
771 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
772 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
776 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
779 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
804 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate() local
809 rate = samsung_get_pll_settings(pll, drate); in samsung_pll46xx_set_rate()
811 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll46xx_set_rate()
816 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
817 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
823 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
828 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
834 /* Set PLL PMS and VSEL values. */ in samsung_pll46xx_set_rate()
835 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
851 /* Set PLL K, MFR and MRR values. */ in samsung_pll46xx_set_rate()
852 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
860 /* Write configuration to PLL */ in samsung_pll46xx_set_rate()
861 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
862 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
863 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
865 /* Wait for PLL lock */ in samsung_pll46xx_set_rate()
866 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); in samsung_pll46xx_set_rate()
895 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate() local
899 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
900 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
935 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate() local
939 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
940 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
973 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate() local
977 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
1014 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate() local
1018 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1042 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate() local
1047 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2550xx_set_rate()
1049 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2550xx_set_rate()
1054 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1060 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1065 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1066 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1068 /* Change PLL PMS values */ in samsung_pll2550xx_set_rate()
1075 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1077 /* Wait for PLL lock */ in samsung_pll2550xx_set_rate()
1078 return samsung_pll_lock_wait(pll, in samsung_pll2550xx_set_rate()
1114 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate() local
1119 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1124 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1137 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate() local
1142 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650x_set_rate()
1144 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650x_set_rate()
1149 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1150 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1152 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1153 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1155 /* Change PLL PMS values */ in samsung_pll2650x_set_rate()
1163 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1167 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1169 /* Wait for PLL lock */ in samsung_pll2650x_set_rate()
1170 return samsung_pll_lock_wait(pll, in samsung_pll2650x_set_rate()
1206 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate() local
1211 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1212 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1228 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate() local
1232 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650xx_set_rate()
1234 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650xx_set_rate()
1239 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1240 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1242 /* Change PLL PMS values */ in samsung_pll2650xx_set_rate()
1256 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1257 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1259 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1260 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1262 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); in samsung_pll2650xx_set_rate()
1291 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll531x_recalc_rate() local
1295 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll531x_recalc_rate()
1296 pll_con8 = readl_relaxed(pll->con_reg + 20); in samsung_pll531x_recalc_rate()
1319 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
1323 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
1324 if (!pll) { in _samsung_clk_register_pll()
1325 pr_err("%s: could not allocate pll clk %s\n", in _samsung_clk_register_pll()
1340 pll->rate_count = len; in _samsung_clk_register_pll()
1341 pll->rate_table = kmemdup_array(pll_clk->rate_table, in _samsung_clk_register_pll()
1342 pll->rate_count, in _samsung_clk_register_pll()
1343 sizeof(*pll->rate_table), in _samsung_clk_register_pll()
1345 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1364 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1365 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1366 if (!pll->rate_table) in _samsung_clk_register_pll()
1378 pll->enable_offs = PLL0822X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1379 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1380 if (!pll->rate_table) in _samsung_clk_register_pll()
1390 if (!pll->rate_table) in _samsung_clk_register_pll()
1398 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1399 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1400 if (!pll->rate_table) in _samsung_clk_register_pll()
1406 pll->enable_offs = PLL0831X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1407 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1408 if (!pll->rate_table) in _samsung_clk_register_pll()
1424 if (!pll->rate_table) in _samsung_clk_register_pll()
1433 if (!pll->rate_table) in _samsung_clk_register_pll()
1439 if (!pll->rate_table) in _samsung_clk_register_pll()
1445 if (!pll->rate_table) in _samsung_clk_register_pll()
1454 pr_warn("%s: Unknown pll type for pll clk %s\n", in _samsung_clk_register_pll()
1458 pll->hw.init = &init; in _samsung_clk_register_pll()
1459 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1460 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1461 pll->con_reg = ctx->reg_base + pll_clk->con_offset; in _samsung_clk_register_pll()
1463 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1465 pr_err("%s: failed to register pll clock %s : %d\n", in _samsung_clk_register_pll()
1467 kfree(pll->rate_table); in _samsung_clk_register_pll()
1468 kfree(pll); in _samsung_clk_register_pll()
1472 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()