Lines Matching refs:GATE
1266 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
1268 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
1270 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
1272 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
1274 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1277 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1280 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1283 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
1286 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1288 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
1290 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1292 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1294 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
1296 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1298 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1300 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1302 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1304 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1306 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1308 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
1310 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
1312 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
1314 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1316 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",
1319 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1322 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1325 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1328 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1330 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
1332 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1334 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1336 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
1338 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1340 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1342 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
1344 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
1346 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
1348 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1351 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
1353 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
1355 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
1357 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1359 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
1361 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1364 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1367 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
1370 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1372 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
1374 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1376 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
1379 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
1381 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
1384 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1386 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1388 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
1390 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
1392 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
1394 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1396 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
1398 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
1400 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
1402 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
1404 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1407 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
1409 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1412 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
1414 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1416 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",
1419 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
1421 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
1423 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",
1426 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
1684 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK,
1687 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1",
1689 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1",
1691 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1",
1693 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
1695 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
1699 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK,
1703 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
1707 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK,
1710 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK,
1713 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK,
1717 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK,
1721 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK,
1725 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK,
1729 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK,
1733 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK,
1737 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK,
1740 GATE(CLK_GOUT_APM_GPC_APM_PCLK,
1743 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK,
1747 GATE(CLK_GOUT_APM_INTMEM_ACLK,
1750 GATE(CLK_GOUT_APM_INTMEM_PCLK,
1753 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK,
1757 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK,
1761 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK,
1765 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK,
1769 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK,
1773 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK,
1778 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK,
1782 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK,
1786 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK,
1790 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK,
1794 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK,
1798 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK,
1802 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK,
1806 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK,
1810 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK,
1814 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK,
1818 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK,
1822 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK,
1827 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK,
1832 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK,
1837 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK,
1840 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK,
1844 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK,
1847 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK,
1850 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK,
1854 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK,
1858 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK,
1863 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2,
1867 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK,
1870 GATE(CLK_GOUT_APM_UASC_APM_ACLK,
1873 GATE(CLK_GOUT_APM_UASC_APM_PCLK,
1876 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK,
1880 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK,
1884 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK,
1887 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK,
1890 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK,
1894 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK,
1897 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
1900 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
1903 GATE(CLK_GOUT_APM_WDT_APM_PCLK,
1906 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
2202 GATE(CLK_GOUT_HSI0_PCLK,
2206 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26,
2211 GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT,
2214 GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK,
2218 GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK,
2221 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
2225 GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK,
2228 GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK,
2231 GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK,
2234 GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK,
2238 GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK,
2243 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK,
2248 GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK,
2252 GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK,
2256 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK,
2260 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK,
2264 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK,
2268 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK,
2272 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
2277 GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK,
2282 GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK,
2287 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
2291 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
2295 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK,
2299 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK,
2303 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK,
2307 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK,
2311 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
2315 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
2319 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26,
2323 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40,
2327 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL,
2332 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK,
2336 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK,
2340 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK,
2344 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK,
2349 GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK,
2354 GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK,
2359 GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK,
2624 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
2629 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
2634 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
2638 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
2642 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
2646 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
2650 GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
2654 GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
2657 GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
2662 GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
2667 GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
2672 GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
2676 GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
2680 GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
2684 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
2688 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
2693 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
2697 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
2702 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
2706 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
2711 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
2715 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
2720 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
2725 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
2730 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
2735 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
2739 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
2743 GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
2747 GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
2751 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
2755 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
2759 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
2763 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
2767 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
2771 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
2775 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
2779 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
2783 GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
2787 GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
2792 GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
2797 GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
2802 GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
2806 GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
2810 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
2814 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
2818 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
2822 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
2826 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
2830 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
2834 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
2838 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
2842 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
2846 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
2850 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
2855 GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
2860 GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
3158 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK,
3162 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK,
3166 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK,
3170 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK,
3174 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK,
3178 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM,
3182 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM,
3186 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK,
3190 GATE(CLK_GOUT_MISC_GIC_GICCLK,
3194 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK,
3198 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK,
3202 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK,
3206 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK,
3210 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK,
3214 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK,
3218 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK,
3222 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK,
3226 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk",
3230 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK,
3234 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK,
3238 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK,
3242 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk",
3246 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK,
3250 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK,
3254 GATE(CLK_GOUT_MISC_PUF_I_CLK,
3258 GATE(CLK_GOUT_MISC_QE_DIT_ACLK,
3262 GATE(CLK_GOUT_MISC_QE_DIT_PCLK,
3266 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK,
3270 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK,
3274 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK,
3278 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK,
3282 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK,
3286 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK,
3290 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK,
3294 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK,
3298 GATE(CLK_GOUT_MISC_QE_SSS_ACLK,
3302 GATE(CLK_GOUT_MISC_QE_SSS_PCLK,
3306 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK,
3310 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK,
3314 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK,
3318 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK,
3322 GATE(CLK_GOUT_MISC_RTIC_I_ACLK,
3326 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk",
3330 GATE(CLK_GOUT_MISC_SPDMA_ACLK,
3334 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK,
3338 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK,
3342 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK,
3346 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK,
3350 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK,
3354 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK,
3358 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK,
3362 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK,
3366 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK,
3370 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK,
3374 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK,
3378 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK,
3382 GATE(CLK_GOUT_MISC_SSS_I_ACLK,
3386 GATE(CLK_GOUT_MISC_SSS_I_PCLK,
3390 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2,
3394 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1,
3398 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK,
3402 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK,
3406 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK,
3410 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK,
3414 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK,
3418 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK,
3796 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
3800 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK,
3804 GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK,
3808 GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK,
3812 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK,
3817 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
3821 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
3825 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
3829 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
3833 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11,
3837 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12,
3841 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13,
3845 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14,
3849 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15,
3853 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
3857 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
3861 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
3865 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
3869 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
3873 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
3877 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
3881 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9,
3885 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0,
3889 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1,
3893 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10,
3897 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11,
3901 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12,
3905 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13,
3909 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14,
3913 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15,
3917 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2,
3921 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3,
3925 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4,
3929 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5,
3933 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6,
3937 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7,
3941 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8,
3945 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9,
3950 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
3954 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
3959 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
3963 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
3967 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK,
3971 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK,
3975 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK,
3979 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK,
3983 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK,
3987 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK,
3991 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK,
3995 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK,
3999 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK,
4003 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK,
4007 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK,
4011 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK,
4015 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
4247 GATE(CLK_GOUT_PERIC1_PCLK,
4251 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
4255 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
4259 GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
4263 GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
4267 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
4271 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
4275 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
4279 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
4283 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
4287 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
4291 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
4295 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
4299 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
4303 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
4307 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
4311 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
4315 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
4319 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
4323 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
4327 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
4331 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
4335 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
4339 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
4343 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
4347 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
4351 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
4355 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
4359 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
4363 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,