Lines Matching +full:0 +full:x2008
23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0
25 #define PLL_LOCKTIME_PLL_SHARED1 0x4
26 #define PLL_LOCKTIME_PLL_SHARED2 0x8
27 #define PLL_LOCKTIME_PLL_SHARED3 0xc
28 #define PLL_CON0_PLL_SHARED0 0x100
29 #define PLL_CON0_PLL_SHARED1 0x120
30 #define PLL_CON0_PLL_SHARED2 0x140
31 #define PLL_CON0_PLL_SHARED3 0x160
32 #define MUX_CMU_CIS0_CLKMUX 0x1000
33 #define MUX_CMU_CIS1_CLKMUX 0x1004
34 #define MUX_CMU_CIS2_CLKMUX 0x1008
35 #define MUX_CMU_CPUCL_SWITCHMUX 0x100c
36 #define MUX_CMU_FSYS1_ACLK_MUX 0x1014
37 #define MUX_PLL_SHARED0_MUX 0x1020
38 #define MUX_PLL_SHARED1_MUX 0x1024
39 #define DIV_CMU_CIS0_CLK 0x1800
40 #define DIV_CMU_CIS1_CLK 0x1804
41 #define DIV_CMU_CIS2_CLK 0x1808
42 #define DIV_CMU_CMU_ACLK 0x180c
43 #define DIV_CMU_CPUCL_SWITCH 0x1810
44 #define DIV_CMU_FSYS0_SHARED0DIV4 0x181c
45 #define DIV_CMU_FSYS0_SHARED1DIV3 0x1820
46 #define DIV_CMU_FSYS0_SHARED1DIV4 0x1824
47 #define DIV_CMU_FSYS1_SHARED0DIV4 0x1828
48 #define DIV_CMU_FSYS1_SHARED0DIV8 0x182c
49 #define DIV_CMU_IMEM_ACLK 0x1834
50 #define DIV_CMU_IMEM_DMACLK 0x1838
51 #define DIV_CMU_IMEM_TCUCLK 0x183c
52 #define DIV_CMU_PERIC_SHARED0DIV20 0x1844
53 #define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848
54 #define DIV_CMU_PERIC_SHARED1DIV36 0x184c
55 #define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850
56 #define DIV_PLL_SHARED0_DIV2 0x1858
57 #define DIV_PLL_SHARED0_DIV3 0x185c
58 #define DIV_PLL_SHARED0_DIV4 0x1860
59 #define DIV_PLL_SHARED0_DIV6 0x1864
60 #define DIV_PLL_SHARED1_DIV3 0x1868
61 #define DIV_PLL_SHARED1_DIV36 0x186c
62 #define DIV_PLL_SHARED1_DIV4 0x1870
63 #define DIV_PLL_SHARED1_DIV9 0x1874
64 #define GAT_CMU_CIS0_CLKGATE 0x2000
65 #define GAT_CMU_CIS1_CLKGATE 0x2004
66 #define GAT_CMU_CIS2_CLKGATE 0x2008
67 #define GAT_CMU_CPUCL_SWITCH_GATE 0x200c
68 #define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018
69 #define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c
70 #define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020
71 #define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024
72 #define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028
73 #define GAT_CMU_IMEM_ACLK_GATE 0x2030
74 #define GAT_CMU_IMEM_DMACLK_GATE 0x2034
75 #define GAT_CMU_IMEM_TCUCLK_GATE 0x2038
76 #define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040
77 #define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044
78 #define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048
79 #define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c
80 #define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054
81 #define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058
82 #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
83 #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
149 PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0),
153 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
157 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
161 PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0),
165 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
167 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
169 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
171 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
189 MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
190 MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
191 MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
192 MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
193 MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
194 MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
195 MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
196 MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
197 MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
198 MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
199 MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
200 MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
204 DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
205 DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
206 DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
207 DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
208 DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
210 DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
211 DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
212 DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
214 DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
216 DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
218 DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
220 DIV_CMU_IMEM_ACLK, 0, 4),
222 DIV_CMU_IMEM_DMACLK, 0, 4),
224 DIV_CMU_IMEM_TCUCLK, 0, 4),
226 "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
228 "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
230 "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
232 "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
233 DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
234 DIV_PLL_SHARED0_DIV2, 0, 4),
235 DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
236 DIV_PLL_SHARED0_DIV3, 0, 4),
238 DIV_PLL_SHARED0_DIV4, 0, 4),
240 DIV_PLL_SHARED0_DIV6, 0, 4),
241 DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
242 DIV_PLL_SHARED1_DIV3, 0, 4),
243 DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
244 DIV_PLL_SHARED1_DIV36, 0, 4),
245 DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
246 DIV_PLL_SHARED1_DIV4, 0, 4),
247 DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
248 DIV_PLL_SHARED1_DIV9, 0, 4),
252 GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
253 CLK_IGNORE_UNUSED, 0),
254 GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
255 CLK_IGNORE_UNUSED, 0),
256 GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
257 CLK_IGNORE_UNUSED, 0),
259 GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
261 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
262 GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
263 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
264 GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
265 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
266 GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
267 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
268 GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
269 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
270 GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
271 CLK_IGNORE_UNUSED, 0),
272 GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
273 CLK_IGNORE_UNUSED, 0),
274 GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
275 CLK_IGNORE_UNUSED, 0),
276 GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
277 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
278 GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
279 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
280 GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
281 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
282 GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
283 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
284 GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
285 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
286 GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
287 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
288 GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
289 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
290 GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
291 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
315 /* Register Offset definitions for CMU_PERIC (0x14010000) */
316 #define PLL_CON0_PERIC_DMACLK_MUX 0x100
317 #define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120
318 #define PLL_CON0_PERIC_PCLK_MUX 0x140
319 #define PLL_CON0_PERIC_TBUCLK_MUX 0x160
320 #define PLL_CON0_SPI_CLK 0x180
321 #define PLL_CON0_SPI_PCLK 0x1a0
322 #define PLL_CON0_UART_CLK 0x1c0
323 #define PLL_CON0_UART_PCLK 0x1e0
324 #define MUX_PERIC_EQOS_PHYRXCLK 0x1000
325 #define DIV_EQOS_BUSCLK 0x1800
326 #define DIV_PERIC_MCAN_CLK 0x1804
327 #define DIV_RGMII_CLK 0x1808
328 #define DIV_RII_CLK 0x180c
329 #define DIV_RMII_CLK 0x1810
330 #define DIV_SPI_CLK 0x1814
331 #define DIV_UART_CLK 0x1818
332 #define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000
333 #define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004
334 #define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008
335 #define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c
336 #define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010
337 #define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014
338 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018
339 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c
340 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020
341 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024
342 #define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028
343 #define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c
344 #define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030
345 #define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034
346 #define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038
347 #define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c
348 #define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040
349 #define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044
350 #define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048
351 #define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c
352 #define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050
353 #define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054
354 #define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058
355 #define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c
356 #define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060
357 #define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064
358 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068
359 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c
360 #define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070
361 #define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074
362 #define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078
363 #define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c
364 #define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080
365 #define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084
366 #define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088
367 #define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c
368 #define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090
369 #define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094
370 #define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098
371 #define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c
372 #define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0
373 #define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4
374 #define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8
375 #define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac
376 #define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0
377 #define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4
378 #define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8
379 #define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc
380 #define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0
381 #define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4
382 #define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8
383 #define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc
384 #define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0
385 #define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4
386 #define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8
387 #define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc
388 #define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0
389 #define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4
390 #define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8
391 #define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec
392 #define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0
393 #define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4
394 #define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8
395 #define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc
396 #define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100
397 #define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104
485 FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
500 MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
501 MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
503 MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
504 MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
505 MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
506 MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
507 MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
508 MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
510 MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
514 DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
515 DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
517 DIV_RGMII_CLK, 0, 4),
518 DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
519 DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
520 DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
521 DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
526 "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
527 GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
528 21, CLK_IGNORE_UNUSED, 0),
530 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
531 GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
532 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
533 GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
534 CLK_IGNORE_UNUSED, 0),
535 GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
536 CLK_IGNORE_UNUSED, 0),
537 GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
538 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
539 GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
540 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
541 GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
542 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
543 GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
544 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
545 GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
546 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
547 GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
548 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
549 GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
550 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
551 GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
552 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
554 "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
555 GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
556 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
558 "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
559 GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
560 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
561 GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
562 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
564 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
566 "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
568 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
570 "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
571 GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
572 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
573 GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
574 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
575 GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
576 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
577 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
578 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
579 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
580 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
581 GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
582 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
584 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
586 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
588 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
590 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
592 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
594 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
596 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
598 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
600 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
602 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
604 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
606 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
608 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
610 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
612 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
614 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
616 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
618 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
620 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
622 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
623 GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
624 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
625 GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
626 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
628 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
630 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
632 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
634 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
636 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
638 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
640 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
642 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
644 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
646 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
648 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
650 GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
652 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
654 GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
655 GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
656 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
674 /* Register Offset definitions for CMU_FSYS0 (0x15010000) */
675 #define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100
676 #define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140
677 #define PLL_CON0_EQOS_RGMII_125_MUX1 0x160
678 #define DIV_CLK_UNIPRO 0x1800
679 #define DIV_EQS_RGMII_CLK_125 0x1804
680 #define DIV_PERIBUS_GRP 0x1808
681 #define DIV_EQOS_RII_CLK2O5 0x180c
682 #define DIV_EQOS_RMIICLK_25 0x1810
683 #define DIV_PCIE_PHY_OSCCLK 0x1814
684 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004
685 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008
686 #define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c
687 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010
688 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014
689 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018
690 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c
691 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020
692 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024
693 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028
694 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c
695 #define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038
696 #define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c
697 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040
698 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044
699 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048
700 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c
701 #define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050
702 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054
703 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058
704 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c
705 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060
706 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064
707 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068
708 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c
709 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070
710 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074
711 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078
712 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c
713 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080
714 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084
715 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088
716 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c
717 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090
718 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094
719 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098
720 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c
721 #define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0
722 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4
723 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8
724 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac
725 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0
726 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4
727 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8
728 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc
729 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0
730 #define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4
792 FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000),
793 FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000),
794 FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000),
803 MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
805 MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p,
807 MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
812 DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4),
813 DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1",
814 DIV_EQS_RGMII_CLK_125, 0, 4),
816 "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4),
817 DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4),
818 DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1",
819 DIV_EQOS_RMIICLK_25, 0, 5),
820 DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1",
821 DIV_PCIE_PHY_OSCCLK, 0, 4),
827 CLK_IGNORE_UNUSED, 0),
831 CLK_IGNORE_UNUSED, 0),
832 GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
833 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
834 GATE(0,
838 CLK_IGNORE_UNUSED, 0),
841 CLK_IGNORE_UNUSED, 0),
844 CLK_IGNORE_UNUSED, 0),
847 CLK_IGNORE_UNUSED, 0),
850 CLK_IGNORE_UNUSED, 0),
851 GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp",
852 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0),
853 GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp",
854 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
855 GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk",
856 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
857 GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp",
858 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
859 GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp",
860 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
861 GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1",
862 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
863 GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk",
864 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
867 CLK_IGNORE_UNUSED, 0),
870 CLK_IGNORE_UNUSED, 0),
873 CLK_IGNORE_UNUSED, 0),
874 GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5",
875 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
876 GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25",
877 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
878 GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
879 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
880 GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
881 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
882 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d",
885 CLK_IGNORE_UNUSED, 0),
886 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1",
889 CLK_IGNORE_UNUSED, 0),
890 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p",
893 CLK_IGNORE_UNUSED, 0),
894 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s",
897 CLK_IGNORE_UNUSED, 0),
898 GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk",
901 CLK_IGNORE_UNUSED, 0),
902 GATE(0,
906 21, CLK_IGNORE_UNUSED, 0),
907 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp",
908 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0),
909 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
910 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0),
915 CLK_IGNORE_UNUSED, 0),
916 GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
919 CLK_IGNORE_UNUSED, 0),
924 CLK_IGNORE_UNUSED, 0),
929 CLK_IGNORE_UNUSED, 0),
930 GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1",
931 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
932 GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk",
933 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0),
934 GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
935 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
937 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
939 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
941 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
943 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
945 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
947 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
949 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
951 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
952 GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE,
953 21, CLK_IGNORE_UNUSED, 0),
955 "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
973 /* Register Offset definitions for CMU_FSYS1 (0x16810000) */
974 #define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100
975 #define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180
976 #define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800
977 #define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804
978 #define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000
979 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004
980 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008
981 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c
982 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c
983 #define GAT_FSYS1_PHY0_OSCCLLK 0x2034
984 #define GAT_FSYS1_PHY1_OSCCLK 0x2038
985 #define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c
986 #define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040
987 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048
988 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c
989 #define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054
990 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c
991 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064
992 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c
993 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070
994 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074
995 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078
996 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c
997 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080
998 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084
999 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088
1000 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c
1001 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4
1002 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8
1003 #define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4
1004 #define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8
1041 FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000),
1042 FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000),
1050 MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p,
1052 MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
1057 DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk",
1058 DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4),
1059 DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk",
1060 DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4),
1064 GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
1065 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1066 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref",
1067 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0),
1068 GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux",
1069 GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0),
1070 GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux",
1071 GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
1072 GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux",
1073 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1074 GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
1075 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1076 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1077 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0),
1078 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
1079 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1080 GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
1081 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1082 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0",
1085 CLK_IGNORE_UNUSED, 0),
1086 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0",
1089 CLK_IGNORE_UNUSED, 0),
1092 CLK_IGNORE_UNUSED, 0),
1093 GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1094 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1095 GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
1096 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0),
1097 GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1098 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1101 CLK_IGNORE_UNUSED, 0),
1104 CLK_IGNORE_UNUSED, 0),
1107 CLK_IGNORE_UNUSED, 0),
1108 GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1109 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1112 CLK_IGNORE_UNUSED, 0),
1115 CLK_IGNORE_UNUSED, 0),
1116 GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
1117 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
1119 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
1121 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
1122 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk",
1123 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0),
1124 GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
1125 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1126 GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
1127 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1145 /* Register Offset definitions for CMU_IMEM (0x10010000) */
1146 #define PLL_CON0_CLK_IMEM_ACLK 0x100
1147 #define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120
1148 #define PLL_CON0_CLK_IMEM_TCUCLK 0x140
1149 #define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800
1150 #define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000
1151 #define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004
1152 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
1153 #define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c
1154 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010
1155 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014
1156 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018
1157 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c
1158 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020
1159 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024
1160 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028
1161 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c
1162 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030
1163 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034
1164 #define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038
1165 #define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c
1166 #define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040
1167 #define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044
1168 #define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048
1169 #define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c
1170 #define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050
1171 #define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054
1172 #define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058
1173 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c
1174 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060
1175 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064
1176 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068
1177 #define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c
1178 #define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070
1179 #define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074
1180 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078
1181 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c
1182 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080
1183 #define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084
1184 #define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088
1185 #define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c
1186 #define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090
1187 #define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094
1188 #define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098
1189 #define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c
1190 #define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0
1191 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4
1192 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8
1193 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac
1194 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0
1195 #define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4
1196 #define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8
1197 #define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc
1198 #define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0
1199 #define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4
1200 #define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8
1201 #define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc
1202 #define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0
1203 #define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4
1204 #define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8
1205 #define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc
1275 MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
1277 MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
1278 MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
1283 DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
1287 GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1288 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1289 GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
1290 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
1291 GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
1292 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1293 GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
1294 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1295 GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
1296 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1297 GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
1298 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1299 GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
1300 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
1301 GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
1302 GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1303 GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
1304 GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1305 GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
1306 GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1309 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1312 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1315 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1318 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1321 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
1322 GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
1323 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
1324 GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
1325 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
1326 GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
1327 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
1328 GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
1329 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
1330 GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
1331 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
1332 GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
1333 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
1334 GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
1335 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
1336 GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
1337 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
1338 GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
1339 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
1340 GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
1341 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
1342 GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
1343 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1344 GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
1345 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1346 GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
1347 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1348 GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
1349 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
1350 GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
1351 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
1352 GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
1353 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
1355 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
1357 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
1358 GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
1359 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1360 GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
1361 GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1362 GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
1363 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1364 GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1365 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1366 GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1367 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1369 GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1370 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
1372 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
1373 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
1376 CLK_IGNORE_UNUSED, 0),
1377 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
1378 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
1379 GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1380 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1381 GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
1382 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1383 GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
1384 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1385 GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
1386 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1387 GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
1388 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1389 GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1390 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1391 GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1392 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1393 GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
1394 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
1395 GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
1396 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1397 GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
1398 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1399 GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
1400 GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1402 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1404 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1406 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1428 /* Register Offset definitions for CMU_MFC (0x12810000) */
1429 #define PLL_LOCKTIME_PLL_MFC 0x0
1430 #define PLL_CON0_PLL_MFC 0x100
1431 #define MUX_MFC_BUSD 0x1000
1432 #define MUX_MFC_BUSP 0x1008
1433 #define DIV_MFC_BUSD_DIV4 0x1800
1434 #define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000
1435 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004
1436 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008
1437 #define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c
1438 #define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010
1439 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018
1440 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c
1441 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028
1442 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c
1443 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030
1444 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034
1445 #define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038
1446 #define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c
1447 #define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040
1448 #define GAT_MFC_BUSD_DIV4_GATE 0x2044
1449 #define GAT_MFC_BUSD_GATE 0x2048
1476 PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0),
1480 PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
1489 MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
1490 MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
1491 MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
1495 DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
1499 GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
1500 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1501 GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
1502 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
1503 GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
1504 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
1505 GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
1506 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1508 GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1509 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
1510 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
1511 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
1512 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
1513 GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
1514 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1515 GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
1516 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1517 GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
1518 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1519 GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
1520 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1521 GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
1522 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1523 GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
1524 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1525 GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
1526 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
1527 GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
1528 GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
1529 GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
1546 /* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
1547 #define PLL_LOCKTIME_PLL_CAM_CSI 0x0
1548 #define PLL_CON0_PLL_CAM_CSI 0x100
1549 #define DIV_CAM_CSI0_ACLK 0x1800
1550 #define DIV_CAM_CSI1_ACLK 0x1804
1551 #define DIV_CAM_CSI2_ACLK 0x1808
1552 #define DIV_CAM_CSI_BUSD 0x180c
1553 #define DIV_CAM_CSI_BUSP 0x1810
1554 #define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
1555 #define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
1556 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
1557 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
1558 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
1559 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
1560 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
1561 #define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
1562 #define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
1563 #define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
1564 #define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
1565 #define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
1566 #define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
1567 #define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
1568 #define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
1569 #define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
1570 #define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
1571 #define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
1572 #define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
1573 #define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
1574 #define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
1575 #define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
1576 #define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
1577 #define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
1578 #define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
1579 #define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
1580 #define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
1581 #define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
1582 #define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
1583 #define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
1584 #define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
1585 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
1586 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
1587 #define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
1588 #define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
1636 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
1640 PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
1647 MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
1651 DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
1652 DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
1653 DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
1654 DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
1655 DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
1659 GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
1660 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1661 GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
1662 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1663 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
1664 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
1665 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
1666 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
1667 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
1668 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
1669 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
1671 CLK_IGNORE_UNUSED, 0),
1672 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
1673 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
1675 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1676 GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1677 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1679 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1680 GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1681 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1683 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1684 GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1685 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1687 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1688 GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1689 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1691 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1692 GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1693 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1695 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1696 GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1697 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1699 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1700 GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1701 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1703 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1704 GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1705 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1707 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1708 GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1709 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1711 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1712 GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1713 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1715 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1716 GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1717 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1719 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1720 GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1721 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1722 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
1725 CLK_IGNORE_UNUSED, 0),
1726 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
1729 CLK_IGNORE_UNUSED, 0),
1730 GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
1731 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1732 GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
1733 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1764 return 0; in fsd_cmu_probe()