Lines Matching +full:0 +full:x10800000
25 /* Register Offset definitions for CMU_TOP (0x11000000) */
26 #define PLL_LOCKTIME_PLL_MMC 0x0004
27 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
28 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
29 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
30 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
31 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
32 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
33 #define PLL_CON0_PLL_MMC 0x0140
34 #define PLL_CON3_PLL_MMC 0x014c
35 #define PLL_CON0_PLL_SHARED0 0x0180
36 #define PLL_CON3_PLL_SHARED0 0x018c
37 #define PLL_CON0_PLL_SHARED1 0x01c0
38 #define PLL_CON3_PLL_SHARED1 0x01cc
39 #define PLL_CON0_PLL_SHARED2 0x0200
40 #define PLL_CON3_PLL_SHARED2 0x020c
41 #define PLL_CON0_PLL_SHARED3 0x0240
42 #define PLL_CON3_PLL_SHARED3 0x024c
43 #define PLL_CON0_PLL_SHARED4 0x0280
44 #define PLL_CON3_PLL_SHARED4 0x028c
45 #define PLL_CON0_PLL_SHARED5 0x02c0
46 #define PLL_CON3_PLL_SHARED5 0x02cc
49 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000
50 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004
51 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
52 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014
55 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018
56 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c
57 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020
58 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
59 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c
65 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040
66 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
67 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048
68 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c
69 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050
70 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054
71 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058
72 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c
73 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060
74 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064
75 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068
76 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c
77 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070
78 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074
79 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078
80 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c
81 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084
83 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088
84 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094
87 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098
88 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c
89 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0
90 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4
91 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8
92 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac
93 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0
94 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4
95 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8
96 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc
97 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0
98 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4
99 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0
102 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4
103 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8
104 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc
105 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0
106 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4
107 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8
108 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec
109 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0
110 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
113 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800
114 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804
115 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808
116 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c
117 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810
118 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814
119 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818
120 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c
121 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
122 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824
123 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
124 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
125 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
126 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834
127 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838
128 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c
129 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
130 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844
131 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848
132 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c
133 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850
134 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854
135 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858
136 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c
137 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860
138 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864
139 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
140 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c
141 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870
142 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874
143 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878
144 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c
145 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880
146 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884
147 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888
148 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c
149 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890
150 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894
151 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898
152 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c
153 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0
154 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4
155 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8
156 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac
157 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0
158 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4
159 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8
160 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc
161 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0
162 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4
163 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8
164 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc
165 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0
166 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4
167 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8
168 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc
169 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0
170 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4
171 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8
172 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec
173 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0
560 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
562 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
566 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3),
568 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3),
572 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2),
576 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
578 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2),
583 0, 2),
586 0, 3),
589 0, 2),
594 0, 2),
597 0, 3),
602 0, 2),
605 0, 3),
609 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
613 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2),
615 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
617 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1),
621 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3),
623 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1),
627 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3),
629 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3),
631 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3),
635 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
639 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
641 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
645 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
649 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
654 0, 2),
657 0, 2),
660 0, 2),
665 0, 2),
668 0, 2),
671 0, 2),
674 0, 2),
678 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3),
682 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2),
684 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2),
688 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
690 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
694 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3),
698 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
700 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
704 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2),
708 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
712 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3),
716 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3),
720 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1),
722 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
726 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1),
728 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
732 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
736 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3),
740 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
744 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3),
752 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
756 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4),
758 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4),
762 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3),
766 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
768 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
773 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
776 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3),
779 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
784 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
787 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3),
792 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
795 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3),
799 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4),
803 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4),
805 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
807 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5),
811 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4),
813 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
817 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4),
819 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4),
821 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4),
825 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4),
829 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
831 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
835 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4),
839 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
843 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
845 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4),
847 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9),
851 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4),
853 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4),
855 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3),
857 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3),
861 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4),
865 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4),
867 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4),
871 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
873 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
877 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4),
881 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
885 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4),
889 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4),
893 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4),
897 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4),
901 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
903 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
907 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
909 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
913 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4),
917 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4),
921 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
925 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4),
930 "mout_shared0_pll", 1, 1, 0),
932 "mout_shared0_pll", 1, 2, 0),
934 "mout_shared0_pll", 1, 3, 0),
936 "mout_shared0_pll", 1, 4, 0),
938 "mout_shared1_pll", 1, 1, 0),
940 "mout_shared1_pll", 1, 2, 0),
942 "mout_shared1_pll", 1, 3, 0),
944 "mout_shared1_pll", 1, 4, 0),
946 "mout_shared2_pll", 1, 1, 0),
948 "mout_shared2_pll", 1, 2, 0),
950 "mout_shared2_pll", 1, 3, 0),
952 "mout_shared2_pll", 1, 4, 0),
954 "mout_shared3_pll", 1, 1, 0),
956 "mout_shared3_pll", 1, 2, 0),
958 "mout_shared3_pll", 1, 3, 0),
960 "mout_shared3_pll", 1, 4, 0),
962 "mout_shared4_pll", 1, 1, 0),
964 "mout_shared4_pll", 1, 2, 0),
966 "mout_shared4_pll", 1, 3, 0),
968 "mout_shared4_pll", 1, 4, 0),
970 "mout_shared5_pll", 1, 1, 0),
972 "mout_shared5_pll", 1, 2, 0),
974 "mout_shared5_pll", 1, 3, 0),
976 "mout_shared5_pll", 1, 4, 0),
1004 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1005 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600
1006 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610
1007 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000
1008 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004
1009 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008
1010 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c
1011 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010
1012 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014
1013 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018
1014 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c
1015 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020
1016 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024
1017 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028
1018 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
1019 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1020 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1021 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1022 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1023 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1024 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1025 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c
1026 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820
1027 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824
1028 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1069 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1071 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1073 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1075 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1077 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1079 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1081 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1),
1083 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1),
1085 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1),
1088 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1091 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1),
1098 0, 4),
1101 0, 4),
1104 0, 4),
1107 0, 4),
1110 0, 4),
1113 0, 4),
1116 0, 4),
1119 0, 4),
1122 0, 4),
1125 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1128 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
1150 return 0; in exynosautov920_cmu_probe()