clk/samsung/clk-exynos7.c

45 PNAME(mout_topc_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
46 PNAME(mout_topc_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
47 PNAME(mout_topc_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
48 PNAME(mout_topc_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
49 PNAME(mout_topc_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
174 	PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
176 	PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
178 	PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
180 	PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
182 	PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
230 PNAME(mout_top0_bus0_pll_user_p)	= { "fin_pll", "sclk_bus0_pll_a" };
231 PNAME(mout_top0_bus1_pll_user_p)	= { "fin_pll", "sclk_bus1_pll_a" };
232 PNAME(mout_top0_cc_pll_user_p)	= { "fin_pll", "sclk_cc_pll_a" };
233 PNAME(mout_top0_mfc_pll_user_p)	= { "fin_pll", "sclk_mfc_pll_a" };
234 PNAME(mout_top0_aud_pll_user_p)	= { "fin_pll", "sclk_aud_pll" };
419 PNAME(mout_top1_bus0_pll_user_p)	= { "fin_pll", "sclk_bus0_pll_b" };
420 PNAME(mout_top1_bus1_pll_user_p)	= { "fin_pll", "sclk_bus1_pll_b" };
421 PNAME(mout_top1_cc_pll_user_p)	= { "fin_pll", "sclk_cc_pll_b" };
422 PNAME(mout_top1_mfc_pll_user_p)	= { "fin_pll", "sclk_mfc_pll_b" };
594 PNAME(mout_aclk_ccore_133_user_p)	= { "fin_pll", "aclk_ccore_133" };
635 PNAME(mout_aclk_peric0_66_user_p)	= { "fin_pll", "aclk_peric0_66" };
636 PNAME(mout_sclk_uart0_user_p)	= { "fin_pll", "sclk_uart0" };
675 	GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
704 PNAME(mout_aclk_peric1_66_user_p)	= { "fin_pll", "aclk_peric1_66" };
705 PNAME(mout_sclk_uart1_user_p)	= { "fin_pll", "sclk_uart1" };
706 PNAME(mout_sclk_uart2_user_p)	= { "fin_pll", "sclk_uart2" };
707 PNAME(mout_sclk_uart3_user_p)	= { "fin_pll", "sclk_uart3" };
708 PNAME(mout_sclk_spi0_user_p)		= { "fin_pll", "sclk_spi0" };
709 PNAME(mout_sclk_spi1_user_p)		= { "fin_pll", "sclk_spi1" };
710 PNAME(mout_sclk_spi2_user_p)		= { "fin_pll", "sclk_spi2" };
711 PNAME(mout_sclk_spi3_user_p)		= { "fin_pll", "sclk_spi3" };
712 PNAME(mout_sclk_spi4_user_p)		= { "fin_pll", "sclk_spi4" };
828 PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
851 	GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
854 	GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
888 PNAME(mout_aclk_fsys0_200_user_p)	= { "fin_pll", "aclk_fsys0_200" };
889 PNAME(mout_sclk_mmc2_user_p)		= { "fin_pll", "sclk_mmc2" };
891 PNAME(mout_sclk_usbdrd300_user_p)	= { "fin_pll", "sclk_usbdrd300" };
892 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p)	= { "fin_pll",
894 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p)	= { "fin_pll",
948 	GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
961 		"fin_pll",
999 PNAME(mout_aclk_fsys1_200_user_p)	= { "fin_pll", "aclk_fsys1_200" };
1000 PNAME(mout_fsys1_group_p)	= { "fin_pll", "fin_pll_26m",
1002 PNAME(mout_sclk_mmc0_user_p)		= { "fin_pll", "sclk_mmc0" };
1003 PNAME(mout_sclk_mmc1_user_p)		= { "fin_pll", "sclk_mmc1" };
1004 PNAME(mout_sclk_ufsunipro20_user_p)  = { "fin_pll", "sclk_ufsunipro20" };
1005 PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
1006 PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
1007 PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
1086 		"fin_pll",
1122 PNAME(mout_aclk_mscl_532_user_p)	= { "fin_pll", "aclk_mscl_532" };
1240 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };