Lines Matching refs:ENABLE_PCLK_PERIC1
1576 #define ENABLE_PCLK_PERIC1 0x0904 macro
1586 ENABLE_PCLK_PERIC1,
1683 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1685 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1688 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1690 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1692 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1694 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1696 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1698 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1700 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1702 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),