Lines Matching +full:0 +full:x10300
21 #define APLL_LOCK 0x0
22 #define APLL_CON0 0x100
23 #define SRC_CPU 0x200
24 #define DIV_CPU0 0x500
25 #define DIV_CPU1 0x504
26 #define GATE_BUS_CPU 0x700
27 #define GATE_SCLK_CPU 0x800
28 #define CLKOUT_CMU_CPU 0xa00
29 #define SRC_MASK_CPERI 0x4300
30 #define GATE_IP_G2D 0x8800
31 #define CPLL_LOCK 0x10020
32 #define DPLL_LOCK 0x10030
33 #define EPLL_LOCK 0x10040
34 #define RPLL_LOCK 0x10050
35 #define IPLL_LOCK 0x10060
36 #define SPLL_LOCK 0x10070
37 #define VPLL_LOCK 0x10080
38 #define MPLL_LOCK 0x10090
39 #define CPLL_CON0 0x10120
40 #define DPLL_CON0 0x10128
41 #define EPLL_CON0 0x10130
42 #define EPLL_CON1 0x10134
43 #define EPLL_CON2 0x10138
44 #define RPLL_CON0 0x10140
45 #define RPLL_CON1 0x10144
46 #define RPLL_CON2 0x10148
47 #define IPLL_CON0 0x10150
48 #define SPLL_CON0 0x10160
49 #define VPLL_CON0 0x10170
50 #define MPLL_CON0 0x10180
51 #define SRC_TOP0 0x10200
52 #define SRC_TOP1 0x10204
53 #define SRC_TOP2 0x10208
54 #define SRC_TOP3 0x1020c
55 #define SRC_TOP4 0x10210
56 #define SRC_TOP5 0x10214
57 #define SRC_TOP6 0x10218
58 #define SRC_TOP7 0x1021c
59 #define SRC_TOP8 0x10220 /* 5800 specific */
60 #define SRC_TOP9 0x10224 /* 5800 specific */
61 #define SRC_DISP10 0x1022c
62 #define SRC_MAU 0x10240
63 #define SRC_FSYS 0x10244
64 #define SRC_PERIC0 0x10250
65 #define SRC_PERIC1 0x10254
66 #define SRC_ISP 0x10270
67 #define SRC_CAM 0x10274 /* 5800 specific */
68 #define SRC_TOP10 0x10280
69 #define SRC_TOP11 0x10284
70 #define SRC_TOP12 0x10288
71 #define SRC_TOP13 0x1028c /* 5800 specific */
72 #define SRC_MASK_TOP0 0x10300
73 #define SRC_MASK_TOP1 0x10304
74 #define SRC_MASK_TOP2 0x10308
75 #define SRC_MASK_TOP7 0x1031c
76 #define SRC_MASK_DISP10 0x1032c
77 #define SRC_MASK_MAU 0x10334
78 #define SRC_MASK_FSYS 0x10340
79 #define SRC_MASK_PERIC0 0x10350
80 #define SRC_MASK_PERIC1 0x10354
81 #define SRC_MASK_ISP 0x10370
82 #define DIV_TOP0 0x10500
83 #define DIV_TOP1 0x10504
84 #define DIV_TOP2 0x10508
85 #define DIV_TOP8 0x10520 /* 5800 specific */
86 #define DIV_TOP9 0x10524 /* 5800 specific */
87 #define DIV_DISP10 0x1052c
88 #define DIV_MAU 0x10544
89 #define DIV_FSYS0 0x10548
90 #define DIV_FSYS1 0x1054c
91 #define DIV_FSYS2 0x10550
92 #define DIV_PERIC0 0x10558
93 #define DIV_PERIC1 0x1055c
94 #define DIV_PERIC2 0x10560
95 #define DIV_PERIC3 0x10564
96 #define DIV_PERIC4 0x10568
97 #define DIV_CAM 0x10574 /* 5800 specific */
98 #define SCLK_DIV_ISP0 0x10580
99 #define SCLK_DIV_ISP1 0x10584
100 #define DIV2_RATIO0 0x10590
101 #define DIV4_RATIO 0x105a0
102 #define GATE_BUS_TOP 0x10700
103 #define GATE_BUS_DISP1 0x10728
104 #define GATE_BUS_GEN 0x1073c
105 #define GATE_BUS_FSYS0 0x10740
106 #define GATE_BUS_FSYS2 0x10748
107 #define GATE_BUS_PERIC 0x10750
108 #define GATE_BUS_PERIC1 0x10754
109 #define GATE_BUS_PERIS0 0x10760
110 #define GATE_BUS_PERIS1 0x10764
111 #define GATE_BUS_NOC 0x10770
112 #define GATE_TOP_SCLK_ISP 0x10870
113 #define GATE_IP_GSCL0 0x10910
114 #define GATE_IP_GSCL1 0x10920
115 #define GATE_IP_CAM 0x10924 /* 5800 specific */
116 #define GATE_IP_MFC 0x1092c
117 #define GATE_IP_DISP1 0x10928
118 #define GATE_IP_G3D 0x10930
119 #define GATE_IP_GEN 0x10934
120 #define GATE_IP_FSYS 0x10944
121 #define GATE_IP_PERIC 0x10950
122 #define GATE_IP_PERIS 0x10960
123 #define GATE_IP_MSCL 0x10970
124 #define GATE_TOP_SCLK_GSCL 0x10820
125 #define GATE_TOP_SCLK_DISP1 0x10828
126 #define GATE_TOP_SCLK_MAU 0x1083c
127 #define GATE_TOP_SCLK_FSYS 0x10840
128 #define GATE_TOP_SCLK_PERIC 0x10850
129 #define TOP_SPARE2 0x10b08
130 #define BPLL_LOCK 0x20010
131 #define BPLL_CON0 0x20110
132 #define SRC_CDREX 0x20200
133 #define DIV_CDREX0 0x20500
134 #define DIV_CDREX1 0x20504
135 #define GATE_BUS_CDREX0 0x20700
136 #define GATE_BUS_CDREX1 0x20704
137 #define KPLL_LOCK 0x28000
138 #define KPLL_CON0 0x28100
139 #define SRC_KFC 0x28200
140 #define DIV_KFC0 0x28500
278 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
279 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
280 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
281 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
282 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
283 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
284 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
285 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
286 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
287 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
288 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
289 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
290 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
291 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
292 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
448 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
453 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
454 FRATE(0, "sclk_pwi", NULL, 0, 24000000),
455 FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
456 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
457 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
462 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
463 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
468 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
469 FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
473 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
474 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
475 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
476 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
478 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
479 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
480 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
481 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
482 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
484 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
485 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
486 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
487 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
488 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
489 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
492 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
497 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
499 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
501 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
502 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
503 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
504 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
507 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
508 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
510 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
512 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
514 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
517 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
518 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
520 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
522 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
525 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
531 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
533 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
535 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
537 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
540 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
541 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
546 GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
548 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
552 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
553 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
556 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
557 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
558 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
559 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
561 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
562 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
564 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
565 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
566 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
568 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
569 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
570 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
571 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
572 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
573 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
577 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
578 CLK_SET_RATE_PARENT, 0),
580 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
589 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
592 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
594 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
596 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
600 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
606 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
607 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
608 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
609 MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
610 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
611 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
613 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
614 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
615 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
616 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
618 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
619 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
621 MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
622 CLK_SET_RATE_PARENT, 0),
624 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
625 SRC_TOP3, 0, 1),
626 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
630 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
632 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
634 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
636 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
638 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
641 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
642 SRC_TOP4, 0, 1),
643 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
645 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
647 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
649 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
651 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
652 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
657 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
658 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
660 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
662 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
665 SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
666 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
673 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
675 CLK_SET_RATE_PARENT, 0),
677 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
678 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
680 CLK_SET_RATE_PARENT, 0),
681 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
682 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
684 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
685 SRC_TOP10, 0, 1),
686 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
690 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
692 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
694 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
696 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
698 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
701 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
702 SRC_TOP11, 0, 1),
703 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
705 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
706 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
708 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
709 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
715 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
717 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
720 SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
721 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
729 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
730 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
731 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
733 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
735 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
739 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
740 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
741 CLK_SET_RATE_PARENT, 0),
747 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
748 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
749 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
750 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
751 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
752 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
753 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
756 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
757 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
758 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
759 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
760 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
761 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
762 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
763 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
764 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
765 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
766 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
767 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
770 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
771 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
772 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
773 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
774 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
778 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
779 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
780 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
781 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
782 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
785 DIV_TOP0, 0, 3),
799 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
818 16, 3, CLK_SET_RATE_PARENT, 0),
827 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
828 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
829 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
844 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
846 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
848 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
851 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
863 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
864 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
866 /* USB3.0 */
867 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
868 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
869 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
870 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
873 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
874 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
875 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
877 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
878 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
881 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
882 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
883 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
884 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
885 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
888 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
889 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
890 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
894 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
895 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
898 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
899 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
900 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
901 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
902 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
905 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
906 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
907 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
910 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
913 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
914 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
917 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
918 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
919 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
920 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
921 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
922 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
923 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
924 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
925 CLK_SET_RATE_PARENT, 0),
926 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
927 CLK_SET_RATE_PARENT, 0),
932 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
933 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
934 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
935 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
936 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
938 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
939 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
940 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
941 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
943 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
944 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
945 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
946 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
947 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
948 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
949 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
950 GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
951 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
952 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
953 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
954 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
955 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
956 GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
958 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
959 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
960 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
961 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
962 GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
963 GATE(0, "aclk166", "mout_user_aclk166",
964 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
966 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
967 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
968 GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
969 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
970 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
971 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
972 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
974 GATE_BUS_TOP, 28, 0, 0),
976 GATE_BUS_TOP, 29, 0, 0),
978 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
979 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
983 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
985 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
987 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
989 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
991 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
993 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
995 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
997 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
999 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1001 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
1003 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
1005 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
1007 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
1010 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
1012 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
1014 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1016 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1018 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1020 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1022 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1026 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1028 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1030 GATE_TOP_SCLK_DISP1, 9, 0, 0),
1032 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1034 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1037 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1038 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1039 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1040 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1041 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1042 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1043 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1044 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1046 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1047 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1048 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1049 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1051 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1055 GATE_IP_PERIC, 0, 0, 0),
1057 GATE_IP_PERIC, 1, 0, 0),
1059 GATE_IP_PERIC, 2, 0, 0),
1061 GATE_IP_PERIC, 3, 0, 0),
1063 GATE_IP_PERIC, 6, 0, 0),
1065 GATE_IP_PERIC, 7, 0, 0),
1067 GATE_IP_PERIC, 8, 0, 0),
1069 GATE_IP_PERIC, 9, 0, 0),
1071 GATE_IP_PERIC, 10, 0, 0),
1073 GATE_IP_PERIC, 11, 0, 0),
1075 GATE_IP_PERIC, 12, 0, 0),
1077 GATE_IP_PERIC, 13, 0, 0),
1079 GATE_IP_PERIC, 14, 0, 0),
1081 GATE_IP_PERIC, 15, 0, 0),
1083 GATE_IP_PERIC, 16, 0, 0),
1085 GATE_IP_PERIC, 17, 0, 0),
1087 GATE_IP_PERIC, 18, 0, 0),
1089 GATE_IP_PERIC, 20, 0, 0),
1091 GATE_IP_PERIC, 21, 0, 0),
1093 GATE_IP_PERIC, 22, 0, 0),
1095 GATE_IP_PERIC, 23, 0, 0),
1097 GATE_IP_PERIC, 24, 0, 0),
1099 GATE_IP_PERIC, 26, 0, 0),
1101 GATE_IP_PERIC, 28, 0, 0),
1103 GATE_IP_PERIC, 30, 0, 0),
1105 GATE_IP_PERIC, 31, 0, 0),
1108 GATE_BUS_PERIC, 22, 0, 0),
1112 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1114 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1115 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1116 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1117 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1118 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1119 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1120 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1121 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1122 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1123 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1124 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1125 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1126 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1127 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1128 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1129 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1130 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1133 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1134 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1135 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1136 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1137 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1139 GATE_IP_GEN, 6, 0, 0),
1140 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1142 GATE_IP_GEN, 9, 0, 0),
1146 GATE_BUS_GEN, 28, 0, 0),
1147 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1151 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1153 GATE_TOP_SCLK_GSCL, 7, 0, 0),
1156 GATE_IP_GSCL0, 4, 0, 0),
1158 GATE_IP_GSCL0, 5, 0, 0),
1160 GATE_IP_GSCL0, 6, 0, 0),
1163 GATE_IP_GSCL1, 2, 0, 0),
1165 GATE_IP_GSCL1, 3, 0, 0),
1167 GATE_IP_GSCL1, 4, 0, 0),
1169 CLK_IS_CRITICAL, 0),
1171 CLK_IS_CRITICAL, 0),
1173 GATE_IP_GSCL1, 16, 0, 0),
1175 GATE_IP_GSCL1, 17, 0, 0),
1179 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1181 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1183 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1185 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1187 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1189 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1191 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1195 GATE_BUS_CDREX0, 0, 0, 0),
1197 GATE_BUS_CDREX0, 1, 0, 0),
1198 GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
1199 SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
1202 GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
1204 GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
1206 GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
1208 GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
1211 GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
1213 GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
1215 GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
1217 GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
1221 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1225 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1226 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1227 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1228 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1229 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1231 GATE_IP_DISP1, 7, 0, 0),
1233 GATE_IP_DISP1, 8, 0, 0),
1235 GATE_IP_DISP1, 9, 0, 0),
1239 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1240 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
1241 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
1242 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
1243 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
1247 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1252 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1253 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1255 GATE_IP_GSCL1, 6, 0, 0),
1257 GATE_IP_GSCL1, 7, 0, 0),
1261 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
1262 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
1263 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
1264 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
1269 CLK_SET_RATE_PARENT, 0),
1273 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1274 { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
1278 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1282 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1283 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1284 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1288 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1289 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
1290 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
1295 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1296 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1297 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1299 GATE_IP_MSCL, 8, 0, 0),
1301 GATE_IP_MSCL, 9, 0, 0),
1303 GATE_IP_MSCL, 10, 0, 0),
1307 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
1311 { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
1312 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
1313 { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
1318 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
1320 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1322 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1326 { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
1403 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1409 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1410 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1436 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1437 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1440 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1444 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1511 { 0 },
1534 { 0 },
1554 { 0 },
1558 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1559 0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d),
1560 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1561 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1565 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1566 0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d),
1567 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1568 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1572 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1584 reg_base = of_iomap(np, 0); in exynos5x_clk_init()