clk/samsung/clk-exynos5250.c

173 PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };
176 PNAME(mout_mpll_p)	= { "fin_pll", "mout_mpll_fout" };
178 PNAME(mout_bpll_p)	= { "fin_pll", "mout_bpll_fout" };
179 PNAME(mout_vpllsrc_p)	= { "fin_pll", "sclk_hdmi27m" };
181 PNAME(mout_cpll_p)	= { "fin_pll", "fout_cpll" };
182 PNAME(mout_epll_p)	= { "fin_pll", "fout_epll" };
183 PNAME(mout_gpll_p)	= { "fin_pll", "fout_gpll" };
184 PNAME(mout_mpll_user_p)	= { "fin_pll", "mout_mpll" };
185 PNAME(mout_bpll_user_p)	= { "fin_pll", "mout_bpll" };
191 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
192 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
193 PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
195 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
196 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
199 PNAME(mout_group1_p)	= { "fin_pll", "fin_pll", "sclk_hdmi27m",
205 PNAME(mout_audio0_p)	= { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
206 				"sclk_uhostphy", "fin_pll",
211 PNAME(mout_audio1_p)	= { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
212 				"sclk_uhostphy", "fin_pll",
217 PNAME(mout_audio2_p)	= { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
218 				"sclk_uhostphy", "fin_pll",
228 	FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
736 	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
738 	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
740 	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
742 	[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
744 	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
746 	[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,