Lines Matching refs:RK3588_PMU1CRU_RESET_OFFSET
23 #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) macro
756 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
757 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
758 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12),
759 RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13),
760 RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
763 RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1),
764 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2),
765 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4),
766 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5),
767 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6),
768 RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
769 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8),
770 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10),
771 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
772 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12),
773 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13),
776 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1),
777 RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2),
778 RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5),
779 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6),
780 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
781 RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10),
782 RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13),
783 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14),
784 RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15),
787 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0),
788 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
789 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12),
790 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13),
791 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15),
794 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0),
795 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1),
796 RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3),
797 RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4),
798 RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5),
799 RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6),
800 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),
801 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8),
802 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9),
803 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10),
806 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3),
807 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
808 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
809 RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),