Lines Matching +full:11 +full:- +full:14
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
44 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
51 RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
52 RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14),
65 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
71 RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14),
84 RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
92 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14),
112 RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
115 RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14),
119 RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
120 RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1),
121 RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2),
122 RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3),
123 RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4),
124 RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5),
125 RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6),
126 RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
127 RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8),
128 RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
129 RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
130 RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11),
131 RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12),
132 RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13),
133 RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
158 RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2),
159 RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5),
160 RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6),
161 RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
162 RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8),
163 RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
164 RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10),
165 RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
166 RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12),
167 RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13),
168 RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14),
169 RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15),
197 RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11),
200 RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14),
214 RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11),
217 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14),
230 RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11),
249 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11),
252 RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14),
266 RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14),
292 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11),
295 RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14),
309 RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14),
348 RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11),
351 RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14),
373 RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11),
382 RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11),
385 RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14),
393 RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14),
414 RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11),
417 RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14),
445 RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11),
448 RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14),
464 RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11),
467 RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14),
482 RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11),
507 RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11),
536 RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14),
558 RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11),
569 RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14),
576 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11),
584 RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11),
596 RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11),
604 RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11),
621 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11),
624 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14),
632 RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14),
648 RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11),
650 RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14),
671 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
674 RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14),
687 RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11),
701 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11),
704 RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM
757 RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
760 RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
771 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
783 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14),
788 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
813 RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
816 RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
826 RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),
829 RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
838 RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),