Lines Matching +full:10 +full:- +full:14
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
43 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10),
52 RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14),
64 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10),
71 RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14),
83 RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
92 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14),
102 RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1),
103 RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2),
104 RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3),
105 RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4),
106 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5),
107 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6),
108 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
109 RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8),
110 RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
111 RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10),
112 RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
113 RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12),
114 RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13),
115 RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14),
116 RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15),
129 RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
133 RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
146 RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10),
158 RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2),
159 RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5),
160 RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6),
161 RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
162 RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8),
163 RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
164 RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10),
165 RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
166 RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12),
167 RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13),
168 RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14),
169 RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15),
180 RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10),
196 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10),
200 RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14),
217 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14),
229 RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10),
248 RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10),
252 RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14),
266 RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14),
291 RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10),
295 RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14),
309 RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14),
347 RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10),
351 RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14),
372 RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10),
381 RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10),
385 RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14),
393 RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14),
413 RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10),
417 RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14),
444 RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10),
448 RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14),
463 RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10),
467 RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14),
481 RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10),
506 RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10),
536 RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14),
557 RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10),
567 RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10),
569 RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14),
583 RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
595 RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10),
603 RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10),
624 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14),
632 RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14),
647 RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10),
650 RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14),
670 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10),
674 RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14),
686 RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10),
700 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10),
704 RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM
718 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM
753 RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10),
756 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
760 RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
770 RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10),
781 RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10),
783 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14),
803 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10),
812 RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
816 RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
825 RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
829 RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
838 RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),