Lines Matching +full:8 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
55 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
56 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
57 RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5),
58 RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6),
59 RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8),
60 RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10),
61 RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
62 RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
65 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
70 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
71 RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
72 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
73 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
74 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
83 RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
84 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
99 RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8),
100 RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
116 RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8),
117 RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
133 RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
140 RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
141 RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
157 RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8),
158 RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
167 RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8),
168 RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
184 RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8),
185 RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
200 RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
211 RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8),
212 RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
235 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
249 RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8),
250 RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
274 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
286 RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
301 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
311 RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8),
312 RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
320 RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
333 RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
355 RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8),
356 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
366 RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8),
375 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8),
376 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
428 RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8),
438 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8),
453 RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8),
454 RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
466 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
476 RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
483 RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8),
484 RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
497 RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
511 RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
530 RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8),
531 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
558 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
562 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
567 RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
568 RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
579 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
595 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
607 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),