clk/rockchip/rst-rk3576.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
29 	RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
40 	RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
41 	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
42 	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
43 	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
44 	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
45 	RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
46 	RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
47 	RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
48 	RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
49 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
50 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
51 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
52 	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
65 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 	RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 	RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 	RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
70 	RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
71 	RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
72 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
73 	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
74 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
75 	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
82 	RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
84 	RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
98 	RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
100 	RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
115 	RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
117 	RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
133 	RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
141 	RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
156 	RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
158 	RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
166 	RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
168 	RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
183 	RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
185 	RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
199 	RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
200 	RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
212 	RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
235 	RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
248 	RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
250 	RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
274 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
286 	RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
300 	RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
310 	RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
312 	RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
320 	RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
332 	RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
333 	RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
343 	RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
354 	RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
356 	RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
365 	RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
376 	RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
394 	RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
410 	RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
427 	RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
437 	RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
452 	RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
454 	RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
465 	RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
466 	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
475 	RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
476 	RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
484 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
497 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
511 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
519 	RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
520 	RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
529 	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
531 	RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
557 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
568 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
578 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
580 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
594 	RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
596 	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
607 	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
619 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
620 	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
638 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
639 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
640 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
641 	RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),