clk/rockchip/rst-rk3576.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
26 	RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
41 	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
47 	RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
65 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 	RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 	RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 	RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
70 	RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
71 	RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
72 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
73 	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
74 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
75 	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
78 	RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
84 	RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
94 	RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3),
100 	RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
112 	RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
117 	RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
129 	RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
133 	RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
141 	RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
152 	RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3),
158 	RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
163 	RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3),
168 	RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
179 	RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3),
185 	RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
196 	RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3),
200 	RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
208 	RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3),
212 	RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
219 	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3),
232 	RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3),
235 	RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
250 	RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
256 	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3),
264 	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3),
274 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
281 	RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3),
286 	RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
297 	RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
308 	RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3),
312 	RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
320 	RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
325 	RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3),
333 	RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
339 	RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3),
347 	RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3),
350 	RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3),
356 	RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
362 	RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3),
372 	RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3),
376 	RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
379 	RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3),
406 	RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3),
417 	RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3),
423 	RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3),
444 	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3),
454 	RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
461 	RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3),
466 	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
476 	RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
484 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
497 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
507 	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3),
511 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
517 	RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
520 	RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
531 	RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
542 	RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3),
548 	RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3),
554 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
565 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
568 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
574 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
580 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
590 	RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
596 	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
604 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
607 	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
608 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
609 	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
610 	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
611 	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
615 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
620 	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),