clk/rockchip/rst-rk3576.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
33 	RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
34 	RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
37 	RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
40 	RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
66 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
93 	RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
111 	RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
128 	RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
138 	RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
151 	RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
178 	RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
195 	RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
218 	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
231 	RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
244 	RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
255 	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
263 	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
280 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
296 	RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
307 	RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
338 	RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
346 	RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
361 	RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
390 	RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
393 	RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6),
394 	RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
395 	RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10),
396 	RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
397 	RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12),
398 	RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13),
399 	RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
400 	RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
405 	RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
416 	RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
443 	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
460 	RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
492 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
506 	RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
541 	RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
547 	RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
573 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
589 	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
602 	RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
603 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
604 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
627 	RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),