clk/rockchip/rst-rk3576.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
30 	RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
51 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
62 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
74 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
78 	RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
79 	RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
80 	RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
81 	RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
82 	RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
83 	RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
84 	RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
85 	RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
86 	RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
87 	RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
88 	RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
102 	RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
105 	RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14),
119 	RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
122 	RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14),
126 	RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
127 	RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
128 	RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
129 	RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
130 	RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4),
131 	RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5),
132 	RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6),
133 	RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
134 	RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12),
135 	RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
143 	RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
145 	RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
160 	RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
170 	RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
186 	RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
189 	RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14),
201 	RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
225 	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14),
239 	RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14),
251 	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
275 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
290 	RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14),
302 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
314 	RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
326 	RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
328 	RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14),
368 	RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
396 	RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
399 	RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
412 	RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
430 	RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
470 	RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14),
478 	RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14),
487 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14),
499 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
502 	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14),
512 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
522 	RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
533 	RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
582 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
598 	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
609 	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
622 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),