clk/rockchip/rst-rk3576.c

14 /* 0x27200000 + 0x0A00 */
15 #define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0x27208000 + 0x0A00 */
17 #define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
18 /* 0x27210000 + 0x0A00 */
19 #define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
20 /* 0x27220000 + 0x0A00 */
21 #define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
33 	RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
55 	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
65 	RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
91 	RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
109 	RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
126 	RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
149 	RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0),
176 	RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0),
193 	RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0),
206 	RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0),
229 	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0),
270 	RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0),
279 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0),
284 	RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0),
294 	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
331 	RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0),
336 	RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0),
388 	RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0),
403 	RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0),
441 	RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0),
458 	RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0),
491 	RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0),
505 	RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0),
553 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
554 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
555 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5),
556 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6),
557 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
558 	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
565 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
566 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4),
567 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
568 	RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
571 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
572 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
573 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
574 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
575 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
576 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
577 	RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
578 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
579 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
580 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
581 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
582 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
583 	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
584 	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
587 	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
602 	RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
634 	RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
649 				      reg_base + RK3576_SOFTRST_CON(0),  in rk3576_rst_init()