Lines Matching refs:RV1126_CLKSEL_CON
88 .reg = RV1126_CLKSEL_CON(1), \
135 .core_reg[0] = RV1126_CLKSEL_CON(0),
225 RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
229 RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
233 RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
237 RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
241 RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
245 RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
249 RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
253 RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
257 RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
261 RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
265 RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
403 RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
412 RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
420 RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
425 RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
430 RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
446 RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
460 RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
463 RV1126_CLKSEL_CON(11), 0,
471 RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
474 RV1126_CLKSEL_CON(13), 0,
482 RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
485 RV1126_CLKSEL_CON(15), 0,
493 RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
496 RV1126_CLKSEL_CON(17), 0,
504 RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
507 RV1126_CLKSEL_CON(19), 0,
516 RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
521 RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
526 RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
531 RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
537 RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
545 RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
551 RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
556 RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
561 RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
566 RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
572 RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
598 RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
604 RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
613 RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
620 RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
630 RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
636 RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
640 RV1126_CLKSEL_CON(28), 0,
646 RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
650 RV1126_CLKSEL_CON(29), 0,
656 RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
659 RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
665 RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
669 RV1126_CLKSEL_CON(32), 0,
675 RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
680 RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
684 RV1126_CLKSEL_CON(34), 0,
690 RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
696 RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
702 RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
706 RV1126_CLKSEL_CON(37), 0,
719 RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
727 RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
730 RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
733 RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
740 RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
747 RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
750 CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
762 RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
770 RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
773 RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
781 RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
792 RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
803 RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
808 RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
815 RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
830 RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
840 RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
848 RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
884 RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
908 RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
1009 RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
1016 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
1019 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,