Lines Matching +full:pmu +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
269 * Clock-Architecture Diagram 2
284 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
289 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
292 GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
302 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
305 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
310 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
316 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
318 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
323 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
325 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
331 GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
337 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
343 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
345 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
347 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
353 GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
355 GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
367 GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
372 GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
375 GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
377 GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
379 GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
381 GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
383 GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
386 GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
392 * Clock-Architecture Diagram 1
399 * Clock-Architecture Diagram 3
405 GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
407 GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
409 GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
416 * Clock-Architecture Diagram 4
422 GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
427 GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
432 GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
436 GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
438 GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
440 GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
442 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
448 GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
450 GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
452 GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
454 GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
457 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
466 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
468 GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
477 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
479 GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
488 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
490 GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
499 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
501 GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
510 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
513 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
518 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
523 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
528 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
534 GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
540 GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
542 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
548 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
553 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
558 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
563 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
569 GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
575 GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
577 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
579 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
581 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
583 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
585 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
587 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
590 GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
593 GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
595 GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
601 GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
610 GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
615 GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
617 GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
622 GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
626 * Clock-Architecture Diagram 6
633 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
643 GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
653 GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
662 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
672 GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
677 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
687 GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
693 GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
699 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
709 GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
712 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
714 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
716 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
723 * Clock-Architecture Diagram 9
735 GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
737 GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
742 GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
744 GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
753 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
755 GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
757 GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
759 GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
766 * Clock-Architecture Diagram 12
776 GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
778 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
787 GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
789 GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
798 GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
800 GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
805 GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
810 GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
812 GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
821 GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
823 GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
825 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
827 GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
832 GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
834 GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
837 GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
842 GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
844 GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
850 GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
854 GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
862 GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
865 GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
871 GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
881 GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
888 * Clock-Architecture Diagram 15
890 GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
892 GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
894 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
896 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
898 GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
900 GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
904 * Clock-Architecture Diagram 3
910 GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
912 GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
914 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
916 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
919 * Clock-Architecture Diagram 4
922 GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
924 GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
926 GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
928 GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
930 GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
932 GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
934 GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
936 GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
938 GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
940 GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
942 GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
944 GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
948 * Clock-Architecture Diagram 6
951 GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
953 GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
957 * Clock-Architecture Diagram 9
960 GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
962 GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
964 GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
968 * Clock-Architecture Diagram 12
971 GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
973 GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
975 GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
977 GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
981 GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
985 GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
989 GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
993 GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
995 GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
999 GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
1001 GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
1005 * Clock-Architecture Diagram 13
1011 GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
1013 GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
1021 GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
1023 GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
1025 GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
1027 GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
1029 GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
1031 GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
1033 GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
1035 GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
1037 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
1039 GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
1041 GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
1045 * Clock-Architecture Diagram 15
1047 GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
1049 GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
1051 GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
1053 GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
1055 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
1088 pr_err("%s: could not map cru pmu region\n", __func__); in rv1126_pmu_clk_init()
1094 pr_err("%s: rockchip pmu clk init failed\n", __func__); in rv1126_pmu_clk_init()
1166 .compatible = "rockchip,rv1126-cru",
1169 .compatible = "rockchip,rv1126-pmucru",
1177 struct device_node *np = pdev->dev.of_node; in clk_rv1126_probe()
1180 init_data = (struct clk_rv1126_inits *)of_device_get_match_data(&pdev->dev); in clk_rv1126_probe()
1182 return -EINVAL; in clk_rv1126_probe()
1184 if (init_data->inits) in clk_rv1126_probe()
1185 init_data->inits(np); in clk_rv1126_probe()
1192 .name = "clk-rv1126",